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AD7691

Rev. 0 | Page 21 of 28

4-Wire CS Mode with Busy Indicator

This mode is usually used when a single AD7691 is connected

to an SPI-compatible digital host, which has an interrupt input,

and it is desired to keep CNV, which is used to sample the

analog input, independent of the signal used to select the data

reading. This requirement is particularly important in

applications where low jitter on CNV is desired.

The connection diagram is shown in Figure 40, and the

corresponding timing is given in Figure 41.

With SDI high, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase and

the subsequent data readback. (If SDI and CNV are low, SDO is

driven low.) Prior to the minimum conversion time, SDI can be

used to select other SPI devices, such as analog multiplexers,

but SDI must be returned low before the minimum conversion

time elapses and then held low for the maximum possible

conversion time to guarantee the generation of the busy signal

indicator. When the conversion is complete, SDO goes from

high impedance to low impedance. With a pull-up on the SDO

line, this transition can be used as an interrupt signal to initiate

the data readback controlled by the digital host. The AD7691

then enters the acquisition phase and powers down. The data

bits are clocked out, MSB first, by subsequent SCK falling edges.

The data is valid on both SCK edges. Although the rising edge

can be used to capture the data, a digital host using the SCK

falling edge can allow a faster reading rate, provided it has an

acceptable hold time. After the optional 19th SCK falling edge,

or SDI going high, whichever is earlier, SDO returns to high

impedance.

DATA IN

IRQ

CLK

CONVERT

CS1

VIO

DIGITAL HOST

47kΩ

CNV

SCK

SDO

SDI

AD7691

Figure 40. 4-Wire CS Mode with Busy Indicator Connection Diagram

SDO

D17

D16

tDIS

SCK

171819

tSCK

tSCKL

tSCKH

tHSDO

tDSDO

tEN

CONVERSION

ACQUISITION

tCONV

tCYC

tACQ

ACQUISITION

SDI

CNV

tSSDICNV

tHSDICNV

Figure 41. 4-Wire CS Mode with Busy Indicator Serial Interface Timing

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