Philips Semiconductors

Product specification

74F138

1-of-8 decoder/demultiplexer

2

February 14, 1991

853–0343 01719

FEATURE

DESCRIPTION

The 74F138 decoder accepts three binary weighted inputs (A0, A1,

A2) and when enabled, provides eight mutually exclusive, active low

outputs (Q0 – Q7). The device features three enable inputs; two

active low (E0, E1) and one active high (E2). Every output will be

high unless E0 and E1 are low and E2 is high. This multiple enable

function allows easy parallel expansion of the device to 1-of-32

(5 lines to 32 lines) decoder with just four 74F138s and one inverter

(see Figure 1). The device can be used as an eight output

demultiplexer by using one of the active low enable inputs as the

data input and the remaining enable inputs as strobes. Enable

inputs not used must be permanently tied to their appropriate active

high or active low state.

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

Q7

Q3

Q4

Q5

Q2

Q0

Q1

A0

A1

E2

A2

E0

E1

9

8

GND

Q6

SF00174

TYPE

TYPICAL

PROPAGATION

DELAY

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F138

5.8ns

13mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

INDUSTRIAL RANGE

PKG DWG #

16-pin plastic DIP

N74F138N

I74F138N

SOT38-4

16-pin plastic SO

N74F138D

I74F138D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

A0 – A2

Address inputs

1.0/1.0

20

µA/0.6mA

E0, E1

Enable inputs (active Low)

1.0/1.0

20

µA/0.6mA

E2

Enable input (active High)

1.0/1.0

20

µA/0.6mA

Q0 – Q7

Data outputs

50/33

1.0mA/20mA

NOTE:

One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

A1 A2

A0

Q2 Q3 Q4 Q5

13 12 11 10

12

3

GND = Pin 8

SF00175

Q1

14

Q0

15

Q6

9

Q7

7

4

5

6

E0

E1

E2

IEC/IEEE SYMBOL

SF00176

DMUX

1

2

4

5

6

15

14

13

12

11

10

9

7

0

0

1

2

G

0

3

3

4

5

6

7

3

2

&