LTC4253 datasheet(21/32 Pages) LINER

21 / 32 page

LTC4253

4253f

APPLICATIO S I FOR ATIO

(Refer to Block Diagram)

Calculate maximum load current: 50W/36V = 1.4A; allow-

ing for 83% converter efficiency, IIN(MAX) = 1.7A.

Calculate RS: from Equation (8) RS = 20mΩ.

Calculate ISHORT-CIRCUIT(MAX): from Equation (9)

ISHORTCIRCUIT(MAX) = 6A.

Select a MOSFET that can handle 6A at 72V: IRF530S.

Calculate CT: from Equation (13) CT = 220nF. Select

CT = 330nF, which gives the circuit breaker time-out

period tMAX = 1.76ms.

Consult MOSFET SOA curves: the IRF530S can handle 6A

at 72V for 5ms, so it is safe to use in this application.

Calculate CSS: using Equations (14) and (15) select

CSS = 68nF.

FREQUENCY COMPENSATION

The LTC4253 typical frequency compensation network for

the analog current limit loop is a series RC (10Ω) and CC

connected from GATE to VEE. Figure 6 depicts the relation-

ship between the compensation capacitor CC and the

MOSFET’s CISS. The line in Figure 6 is used to select a

starting value for CC based upon the MOSFET’s CISS

specification. Optimized values for CC are shown for

several popular MOSFETs. Differences in the optimized

value of CC versus the starting value are small. Neverthe-

less, compensation values should be verified by board

level short-circuit testing.

As seen in Figure 5, at the onset of a short-circuit event, the

input supply voltage can ring dramatically due to series

inductance. If this voltage avalanches the MOSFET, cur-

rent continues to flow through the MOSFET to the output.

The analog current limit loop cannot control this current

flow and therefore the loop undershoots. This effect

cannot be eliminated by frequency compensation. A zener

diode is required to clamp the input supply voltage and

prevent MOSFET avalanche.

SENSE RESISTOR CONSIDERATIONS

For proper circuit breaker operation, Kelvin-sense PCB

connections between the sense resistor and the LTC4253’s

VEE and SENSE pins are strongly recommended. The

drawing in Figure 7 illustrates the correct way of making

connections between the LTC4253 and the sense resistor.

PCB layout should be balanced and symmetrical to mini-

mize wiring errors. In addition, the PCB layout for the

sense resistor should include good thermal management

techniques for optimal sense resistor power dissipation.

TIMING WAVEFORMS

System Power-Up

Figure 8 details the timing waveforms for a typical power-

up sequence in the case where a board is already installed

in the backplane and system power is applied abruptly. At

MOSFET CISS (pF)

4253 F06

2000

4000

6000

8000

IRF530

IRF540

IRF740

IRF3710

MTY100N10E

CURRENT FLOW

FROM LOAD

CURRENT FLOW

TO –48V BACKPLANE

SENSE RESISTOR

TRACK WIDTH W:

0.03" PER AMP

ON 1 OZ COPPER

SENSE

VEE

4253 F07

Figure 6. Recommended Compensation

Capacitor CC vs MOSFET CISS

Figure 7. Making PCB Connections to the Sense Resistor

LTC4253 датащи(PDF) 21 Page - Linear Technology

LTC4253 датащи(HTML) 21 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

датащи скачать

ссылки URL