Philips Semiconductors

Product specification

74ALVT16899

2.5V/3.3V 18-bit latched transceiver with 16-bit parity

generator/checker (3-State)

1998 Jun 30

5

BLOCK DIAGRAM

1

0

mux

9–bit

Output

Buffer

OE

9–bit

Output

Buffer

9–bit

Transparent

Latch

LE

Parity

Generator

Parity

Generator

1

0

mux

OE

9–bit

Transparent

Latch

LE

OEB

LEA

A0

A1

A2

A3

A4

A5

A6

A7

APAR

OEA

SEL

ODD/

EVEN

LEB

B7

BPAR

B6

B5

B4

B3

B2

B1

B0

ERRA

ERRB

SH00084

(1 of 2 parity blocks)

FUNCTION TABLE

INPUTS

OPERATING MODE

OEB

OEA

SEL

LEA

LEB

H

H

X

X

X

3-State A bus and B bus (input A & B simultaneously)

H

L

L

L

H

B

→ A, transparent B latch, generate parity from B0 - B7, check B bus parity

H

L

L

H

H

B

→ A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity

H

L

L

X

L

B

→ A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity

H

L

H

X

H

B

→ A, transparent B latch, parity feed-through, check B bus parity

H

L

H

H

H

B

→ A, transparent A & B latch, parity feed-through, check A & B bus parity

L

H

L

H

X

A

→ B, transparent A latch, generate parity from A0 - A7, check A bus parity

L

H

L

H

H

A

→ B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity

L

H

L

L

X

A

→ B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity

L

H

H

H

L

A

→ B, transparent A latch, parity feed-through, check A bus parity

L

H

H

H

H

A

→ B, transparent A & B latch, parity feed-through, check A & B bus parity

L

L

X

X

X

Output to A bus and B bus (NOT ALLOWED)

H = High voltage level

L

= Low voltage level

X = Don’t care