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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STW81102AT датащи(PDF) 19 Page - STMicroelectronics |
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STW81102AT датащи(HTML) 19 Page - STMicroelectronics |
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19 / 43 page  STW81102 General description 19/43 Figure 17. PFD diagram 4.1.6 Lock detect This signal indicates that the difference between rising edges of both UP and DOWN PFD signals is found to be shorter than the fixed delay (roughly 5 ns). Lock Detect signal is high when the PLL is locked. When Power Down is activated, Lock Detect is let to high level (Lock Detect consumes current only during PLL transients). 4.1.7 Charge pump This block drives two matched current sources, Iup and Idown, which are controlled respectively by UP and DOWN PFD outputs. The nominal value of the output current is controlled by an external resistor (to be connected to the REXT input pin) and a selection among 8 by a 3 bit word. The minimum value of the output current is: IMIN = 2*VBG/REXT (VBG~1.17 V) Note: The current is output on pin ICP. During the VCO auto calibration, ICP and VCTRL pins are forced to VDD/2 D FF R Fref VDD R D FF Fref VDD Delay Up Down ABL Table 7. Current value vs selection CPSEL2 CPSEL1 CPSEL0 Current Value for REXT=4.7 K Ω 000 IMIN 0.5 mA 001 2*IMIN 1.0 mA 010 3*IMIN 1.5 mA 011 4*IMIN 2.0 mA 100 5*IMIN 2.5 mA 101 6*IMIN 3.0 mA 110 7*IMIN 3.5 mA 111 8*IMIN 4.0 mA |
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