11

LTC2600/LTC2610/LTC2620

2600fa

Table 1.

COMMAND*

C3

C2

C1

C0

0000

Write to Input Register n

0001

Update (Power Up) DAC Register n

0010

Write to Input Register n, Update (Power Up) All n

0011

Write to and Update (Power Up) n

0100

Power Down n

1111

No Operation

ADDRESS (n)*

A3

A2

A1

A0

0000

DAC A

0001

DAC B

0010

DAC C

0011

DAC D

0100

DAC E

0101

DAC F

0110

DAC G

0111

DAC H

1111

All DACs

Serial Interface

The CS/LD input is level triggered. When this input is taken

low, it acts as a chip-select signal, powering-on the SDI

and SCK buffers and enabling the input shift register. Data

(SDI input) is transferred at the next 24 rising SCK edges.

The 4-bit command, C3-C0, is loaded first; then the 4-bit

DAC address, A3-A0; and finally the 16-bit data word. The

data word comprises the 16-, 14- or 12-bit input code,

ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits

(LTC2600, LTC2610 and LTC2620 respectively). Data can

only be transferred to the device when the CS/LD signal is

low.The rising edge of CS/LD ends the data transfer and

causes the device to carry out the action specified in the

24-bit input word. The complete sequence is shown in

Figure 2a.

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 1. The first four commands in the table

consist of write and update operations. A write operation

loads a 16-bit data word from the 32-bit shift register into

the input register of the selected DAC, n. An update

operation copies the data word from the input register to

the DAC register. Once copied into the DAC register, the

data word becomes the active 16-, 14- or 12-bit input

code, and is converted to an analog voltage at the DAC

output. The update operation also powers up the selected

DAC if it had been in power-down mode. The data path and

registers are shown in the block diagram.

While the minimum input word is 24 bits, it may optionally

be extended to 32 bits. To use the 32-bit word width,

8 don’t-care bits are transferred to the device first, fol-

lowed by the 24-bit word as just described. Figure 2b

OPERATIO

Power-On Reset

The LTC2600/LTC2610/LTC2620 clear the outputs to zero

scale when power is first applied, making system initializa-

tion consistent and repeatable.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2600/

2610/2620 contain circuitry to reduce the power-on glitch:

the analog outputs typically rise less than 10mV above

zero scale during power on if the power supply is ramped

to 5V in 1ms or more. In general, the glitch amplitude

decreases as the power supply ramp time is increased.

See Power-On Reset Glitch in the Typical Performance

Characteristics section.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range

– 0.3V

Ratings). Particular care should be taken to observe these

limits during power supply turn-on and turn-off sequences,

Transfer Function

The digital-to-analog transfer function is

V

k

V

OUT IDEAL

N

REF









2

where k is the decimal equivalent of the binary DAC input

(Pin 6).

*Command and address codes not shown are reserved and should not be used.