2

AT49F008A(T)/8192A(T)

1199G–FLASH–11/02

AT49F8192A(T) TSOP Top View

Type 1

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5

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48

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A15

A14

A13

A12

A11

A10

A9

A8

NC

NC

WE

RESET

NC

NC

NC

A18

A17

A7

A6

A5

A4

A3

A2

A1

A16

BYTE

GND

I/O15 / A-1

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

OE

GND

CE

A0

AT49F008A(T) TSOP Top View

Type 1

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40

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23

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21

A16

A15

A14

A13

A12

A11

A9

A8

WE

RESET

NC

RDY/BUSY

A18

A7

A6

A5

A4

A3

A2

A1

A17

GND

NC

A-1

A10

I/O7

I/O6

I/O5

I/O4

VCC

VCC

NC

I/O3

I/O2

I/O1

I/O0

OE

GND

CE

A0

AT49F8192A(T) SOIC (SOP) Top View

1

2

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5

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22

44

43

42

41

40

39

38

37

36

35

34

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32

31

30

29

28

27

26

25

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23

NC

A18

A17

A7

A6

A5

A4

A3

A2

A1

A0

CE

GND

OE

I/O0

I/O8

I/O1

I/O9

I/O2

I/O10

I/O3

I/O11

RESET

WE

A8

A9

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

Note:

“•” denotes a white dot marked on the package.

The device is erased by executing the Erase command sequence; the device internally con-

trols the erase operation. The memory is divided into four blocks for erase operations. There

are two 4K word parameter block sections: the boot block, and the main memory array block.

The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 8K word boot block section includes a reprogramming lockout feature to provide

data integrity. This feature is enabled by a command sequence. Once the boot block program-

ming lockout feature is enabled, the data in the boot block cannot be changed when input

levels of 5.5 volts or less are used. The boot sector is designed to contain user secure code.

For the AT49F8192A(T), the BYTE pin controls whether the device data I/O pins operate in

the byte or word configuration. If the BYTE pin is set at a logic “1” or left open, the device is in

word configuration, I/O0 - I/O15 are active and controlled by CE and OE.

If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins

I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-

stated and the I/O15 pin is used as an input for the LSB (A-1) address function.