REV. 0

–15–

AD7453

If the throughput rate = 100 kSPS, then the cycle time = 10

ms and

the average power dissipated during each cycle is

266 10

7 25

192

./

.

.

mW

mW

normal operation is 3.3 mW max.

The AD7453 can now be said to dissipate 3.3 mW for 2.66

ms*

during each conversion cycle.

The average power dissipated during each cycle with a through-

put rate of 100 kSPS is therefore

266 10

3 3

0 88

./

.

.

mW

mW

This is how the power numbers in Figure 16 are calculated.

THROUGHPUT (kSPS)

100

0

350

0.01

50

100

150

200

250

300

0.1

1

10

Figure 16. Power vs. Throughput Rate for Power-

Down Mode

For throughput rates above 320 kSPS, it is recommended that

for optimum power performance, the serial clock frequency is

reduced.

MICROPROCESSOR AND DSP INTERFACING

The serial interface on the AD7453 allows the part to be con-

nected directly to a range of different microprocessors. This

section explains how to interface the AD7453 with some of

the more common microcontroller and DSP serial interface

protocols.

AD7453 to ADSP-21xx

The ADSP-21xx family of DSPs are interfaced directly to the

AD7453 without any glue logic required.

The SPORT control register should be set up as follows:

TFSW = RFSW = 1

Alternate Framing

INVRFS = INVTFS = 1

Active Low Frame Signal

DTYPE = 00

Right Justify Data

SLEN = 1111

16-Bit Data Words

ISCLK = 1

Internal Serial Clock

TFSR = RFSR = 1

Frame Every Word

IRFS = 0

ITFS = 1

To implement the power-down mode, SLEN should be set to

1001 to issue an 8-bit SCLK burst.

The connection diagram is shown in Figure 17. The ADSP-21xx

has the TFS and RFS of the SPORT tied together, with TFS

set as an output and RFS set as an input. The DSP operates in

alternate framing mode and the SPORT control register is set

up as described. The frame synchronization signal generated on

the TFS is tied to

CS, and, as with all signal processing applica-

tions, equidistant sampling is necessary. However, in this example,

the timer interrupt is used to control the sampling rate of the

ADC, and, under certain conditions, equidistant sampling may

not be achieved.

CS

SCLK

SDATA

110

16

1

10

16

PART BEGINS

TO POWER UP

THE PART IS FULLY POWERED

INVALID DATA

VALID DATA

A

Figure 15. Exiting Power-Down Mode

*This figure assumes a very short time to enter power-down mode. This will

increase as the burst of clocks used to enter the power down mode is

increased.