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CS5825
Century Semiconductor Inc.
page 4 of 13
FUNCTIONAL DESCRIPTION
Serial-In Parallel-Out 7-Bit Shift Register
It receives the serial data from the transmitter. It uses the 7xclk to strobe the serial data and sends 7-bit parallel
data with input clock’s frequency.
Phase Lock Loop and Phase Aligner
The PLL generates the seven times input clock which is used for deserialized. The phase aligner is used for
synchronous the input clock and output.
Control logic
There are two modes in this circuit. One is normal mode, and another is power down mode. Two modes are
controlled by the control signal “SHTDNN”. If SHTDNN is high, the circuit is in the normal mode, else if low, the
circuit is in the power down mode. In the power down mode, every block is off to make sure the least power
consumption.
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