LTC3313 datasheet(11/28 Pages) AD

11 / 28 page

LTC3313

Rev. 0

For more information www.analog.com

OPERATION

Voltage Regulation

The LTC3313 is a monolithic, constant frequency, current

mode step-down DC/DC converter. An oscillator turns on

the internal top power switch at the beginning of each

clock cycle. Current in the inductor increases until the

top switch current comparator trips and turns off the top

power switch. The peak inductor current at which the top

switch turns off is controlled by the voltage on the ITH

node. The error amplifier servos the ITH node by compar-

ing the voltage on the FB node with an internal 500mV

reference. When the load current increases, it causes a

reduction in the feedback voltage relative to the reference

leading the error amplifier to raise the ITH voltage until the

average inductor current matches the new load current.

When the top power switch turns off, the synchronous

power switch turns on until the next clock cycle begins

or, if in pulse-skipping mode, until the inductor current

falls to zero. If overload conditions result in excessive

current flowing through the bottom switch, the next clock

cycle will be delayed until the switch current returns to

a safe level.

On the LTC3313, the output voltage is resistively divided

externally to create a feedback voltage for the regulator.

In high current operation, a ground offset may be pres-

ent between the LTC3313 local ground and ground at the

load. To overcome this offset, AGND should have a Kelvin

connection to the load ground, and the lowest potential

node of the resistor divider should be connected to AGND.

The internal error amplifier senses the difference between

this feedback voltage and a 0.5V AGND-referenced volt-

age. This scheme overcomes any ground offsets between

local ground and remote output ground, resulting in a

more accurate output voltage. The LTC3313 allows for

remote output ground deviations as much as ±100mV

with respect to local ground.

If the EN pin is low, the LTC3313 is shut down and in a low

quiescent current state. When the EN pin is above its thresh-

old, the switching regulator will be enabled.

Silent Switcher

The LTC3313 uses Silent Switcher 1 technology, allowing

fast switching edges for high efficiency at high switching

frequencies, while simultaneously achieving good EMI

performance. Ceramic capacitors on VIN keep all the fast

AC current loops small, improving EMI performance.

Synchronizing the Oscillator to an External Clock

The LTC3313’s internal oscillator is synchronized through

an internal PLL circuit to an external frequency by apply-

ing a square wave clock signal to the MODE/SYNC pin.

During synchronization, the top power switch turn-on is

locked to the rising edge of the external frequency source.

While synchronizing, the switcher operates in forced con-

tinuous mode. The slope compensation is automatically

adapted to the external clock frequency.

After detecting an external clock on the first rising edge

of the MODE/SYNC pin, the internal PLL gradually adjusts

its operating frequency to match the frequency and phase

of the signal on the MODE/SYNC pin. When the external

clock is removed, the LTC3313 detects the absence of

the external clock within approximately 20µs. During this

time, the PLL will continue to provide clock cycles. Once

the external clock removal has been detected, the oscilla-

tor gradually adjusts its operating frequency back to the

2MHz default frequency.

Mode Selection

The MODE/SYNC pin either synchronizes the switching

frequency to an external clock, is a clock output, or sets

the PWM mode. The PWM mode of operation is either

pulse-skipping or forced continuous. See Table 6 in the

Applications Information section. In pulse-skipping mode,

switching cycles are skipped at light loads to regulate the

output voltage. During forced continuous mode, the top

switch turns on every cycle and light load regulation is

achieved by allowing negative inductor current.

Output Power Good

Comparators monitoring the FB node voltage pull the

PGOOD pin low if the output voltage varies from the

nominal set point or if a fault condition is present. The

comparator includes voltage hysteresis. A time delay to

report PGOOD is used to filter short duration output volt-

age transients.

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