4/11/01; v.0.9

Alliance Semiconductor

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AS4C4M4F0

AS4C4M4F1

®

Functional description

The AS4C4M4F0 and AS4C4M4F1 are high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) devices organized as

4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques resulting in high

speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for

use as main memory in PC, workstation, router and switch applications.

These devices feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at

very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the

falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of

column addresses prior to CAS assertion.

Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:

•RAS-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.

• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with

previous valid data.

•CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.

Outputs are high-impedence (OE and WE are don't care).

• Normal read or write cycles refresh the row being accessed.

• Self-refresh cycles

Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:

•RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.

• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with

previous valid data.

•CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.

Outputs are high-impedence (OE and WE are don't care).

• Normal read or write cycles refresh the row being accessed.

• Self-refresh cycles

The AS4C4M4F0 and AS4C4M4F1 are available in the standard 24/26-pin plastic SOJ and 24/26-pin plastic TSOP packages. The

AS4C4M4F0 and AS4C4M4F1 operate with a single power supply of 5V ± 0.5V and provide TTL compatible inputs and outputs.

Logic block diagram for 4K refresh

RAS clock

generator

4096 × 1024 × 4

Array

(16,777,216)

Sense amp

A0

A1

A2

A3

A4

A5

A6

A7

GND

A8

Column decoder

Data

I/O

buffers

OE

RAS

CAS

WE clock

generator

WE

I/O0 to I/O3

CAS clock

generator

A9

A10

A11