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XRT83SL216 датащи(PDF) 13 Page - Exar Corporation |
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XRT83SL216 датащи(HTML) 13 Page - Exar Corporation |
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13 / 41 page ![]() xr PRELIMINARY XRT83SL216 REV. P1.0.3 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 11 CONTROL FUNCTION NAME PIN TYPE DESCRIPTION JASEL0 JASEL1 G13 H13 I Jitter Attenuator Select: The Jitter Attenuator can be slected to be in the Transmit or Receive path. NOTE: Internally pulled "High" with a 50k Ω resistor. MCLK L6 I Master Clock Input This pin is used as the internal reference to the LIU. This clock must be 2.048MHz +/-50ppm. JTAG SECTION NAME PIN TYPE DESCRIPTION TCK G5 I JTAG Test Clock input, Boundary Scan Clock input: TDI G4 I JTAG Test Data input, Boundary Scan Test Data Input: NOTE: Internally pulled "High" with a 50k Ω resistor. TDO H5 O JTAG Test Data output: Boundary Scan Test Data Output: TMS G6 I JTAG Test Mode Select, Boundary Scan Test Mode Select input pin: NOTE: Internally pulled "High" with a 50k Ω resistor. TRST H4 I JTAG Test Mode Reset, Boundary Scan Mode Reset Input pin: NOTE: This input pin should be pulled "Low" for normal operation. Internally pulled "High" with a 50k Ω resistor. JASEL1 JASEL0 0 JA Select is enabled through µP Control JA in Rx Path JA in Tx Path JA Disabled 1 1 0 1 1 0 0 Jitter Attenuator State |
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