XRT79L74 datasheet(21/70 Pages) EXAR

21 / 70 page

PRELIMINARY

XRT79L74

4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

REV. P1.0.0

TxUClav/

TxPPA

Transmit UTOPIA Interface - Cell Available Output Pin/Transmit POS-PHY

Interface - Packet Data Available Output pin:

The exact function of this output pin depends upon whether the XRT79L74

device has been configured to operate in the ATM UNI or PPP Mode.ATM UNI

Mode - TxUClav - Transmit UTOPIA Interface - Cell Space Available Indicator

Output pin:This output pin supports data flow control between the ATM Layer

Processor and the Transmit UTOPIA Interface block. This signal is asserted

(e.g., driven "high") whenever the TxFIFO is capable of receiving at least one

more full ATM cell of data from the ATM Layer processor. This signal is negated

(e.g., driven "low"), if the TxFIFO is not capable of receiving one more full ATM

cell of data from the ATM Layer processor. The exact behavior of the "TxUClav"

output pin, as a function of "UTOPIA Level" is presented below.

Multi-PHY Operation - UTOPIA Level 2:

When the XRT79L74 device is operating in a Multi-PHY Application and is con-

figured to operate in the UTOPIA Level 2 Mode, then this signal will be tri-stated

until the TxUClk cycle following the assertion of a valid address on the Transmit

UTOPIA Address bus input pins (e.g., when the contents on the Transmit UTO-

PIA Address bus pins, TxUAddr[4:0], match that which have been assigned to

this particular Transmit UTOPIA Interface block). Afterwards, this output pin will

be driven either "high" or "low" depending upon the current fill status of the

TxFIFO.

Multi-PHY Operation - UTOPIA Level 3:

When the XRT79L74 device is operating in a Multi-PHY Application, then this

signal will be tri-stated until two TxUClk cycles following the assertion of a valid

address on the Transmit UTOPIA Address bus input pins (e.g., if the contents of

the Transmit UTOPIA Address bus input pins, TxUAddr[4:0], match that which

have been assigned to this particular Transmit UTOPIA Interface block). After-

wards, this output pin will be driven either "high" or "low" depending upon the

current fill status of the RxFIFO.

PPP Mode - TxPPA

Transmit POS-PHY Interface Packet Space Available Indicator OutputThe

XRT79L74 device will drive this output pin "high" whenever a (programmable)

number of bytes of empty space is available (for writing more PPP packet data)

into the TxFIFO. The exact behavior of the TxPPA output pin, as a function of

"POS-PHY Level" is presented below.

POS-PHY Level 2:

When the XRT79L74 device is configured to operate in the POS-PHY Level 2

Mode, then this signal will be tri-stated until the TxPClk cycle following the asser-

tion of a valid address on the Transmit POS-PHY Address bus input pins (e.g., if

the contents on the Transmit POS-PHY Address bus pins, TxPAddr[4:0], match

that which have been assigned to this particular Transmit POS-PHY Interface

block). Afterwards, this output pin will be driven either "high" or "low" depending

upon the current fill status of the TxFIFO.

POS-PHY Level 3:

When the XRT79L74 device is configured to operate in the POS-PHY Level 3

Mode, then this signal will be tri-stated until two TxPClk cycles following the

assertion of a valid address on the Transmit POS-PHY Address Bus input pins

(e.g., if the contents on the Transmit POS-PHY Address bus pins, TxPAddr[4:0],

match that which have been assigned to this particular Transmit POS-PHY Inter-

face block). Afterwards, this output pin will be driven either "high" or "low"

depending upon the current fill status of the TxFIFO.

PIN #NAME

TYPE

DESCRIPTION

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