XRT73L06 datasheet(21/63 Pages) EXAR

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XRT73L06

SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

REV. 1.0.2

2.2

Adaptive Gain Control (AGC)

The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat

losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB. The peak

detector provides feedback to the equalizer before slicing occurs.

2.3

Receive Equalizer

The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of

up to 900 feet of coaxial cable (1300 feet for E3). The Equalizer also boosts the high frequency content of the

signal to reduce Inter-Symbol Interference (ISI) so that the slicer slices the signal at 50% of peak voltage to

generate Positive and Negative data. The equalizer can be disabled by programming the appropriate register.

FIGURE 7. ACG/EQUALIZER BLCOK DIAGRAM

2.3.1

Recommendations for Equalizer Settings

The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/

STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable,

the Equalizer can be enabled. However, for square-shaped pulses such as E3 or for DS3/STS-1 high pulses

(that does not meet the pulse template requirements), it is recommended that the Equalizer be disabled for

cable length less than 300 feet. This would help to prevent over-equalization of the signal and thus optimize

the performance in terms of better jitter transfer characteristics. The Equalizer also contains an additional 20

dB gain stage to provide the line monitoring capability of the resistively attenuated signals which may have

20dB flat loss. The equalizer gain mode can be enabled by programming the appropriate register.

NOTE: The results of extensive testing indicate that even when the Equalizer was enabled, regardless of the cable length,

the integrity of the E3 signal was restored properly over 0 to 12 dB cable loss at Industrial Temperature.

2.4

Clock and Data Recovery

The Clock and Data Recovery Circuit extracts the embedded clock, RxClk_n from the sliced digital data stream

and provides the retimed data to the B3ZS (HDB3) decoder. The Clock Recovery PLL can be in one of the

following two modes:

2.4.1

Data/Clock Recovery Mode

In the presence of input line signals on the RTIP_n and RRing_n input pins and when the frequency difference

between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on

the RxClk_n out pins is the Recovered Clock signal.

2.4.2

Training Mode

In the absence of input signals at RTIP_n and RRing_n pins, or when the frequency difference between the

recovered line clock signal and the reference clock applied on the ExClk_n input pins exceed 0.5%, a Loss of

Lock condition is declared by toggling RLOL_n output pin “High” or setting the RLOL_n bit to “1” in the control

AGC/

Equalizer

Peak Detector

LOS

Detector

Slicer

RTIP_n

RRing_n

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