PFS5178F-TL datasheet(3/25 Pages) POWERINT

3 / 25 page

Rev. C 03/22

PFS5173-5178/5274

www.power.com

Pin Functional Description

VALLEY SENSING (VS) Pin (Pin 1)

This pin is used to sense voltage on the auxiliary winding of the PFC

inductor. The VS pin is connected to the auxiliary winding on a PFC

inductor through an external resistor. The voltage on the auxiliary

winding on a PFC inductor provides the controller information about

the drain voltage. The external resistor is used to limit the current

through VS pin and for fine adjustment of timing for valley switching.

SIGNAL GROUND (G) Pin (Pin 2, 13)

Discrete components used in the feedback circuit, including loop

compensation, decoupling capacitors for the BIAS POWER (VCC),

REFERENCE (REF) and VOLTAGE MONITOR (V) must be referenced to

the SIGNAL GROUND (G) pin. The SIGNAL GROUND pin is also

connected to the exposed pad of the device. The SIGNAL GROUND

pin should not be tied directly to the SOURCE pin external to the IC.

T Pin (Pin3)

Must be connected to REF pin.

VOLTAGE MONITOR (V) Pin (Pin 4)

The VOLTAGE MONITOR pin is tied to the rectified high-voltage DC

rail through a 100:1, 1% high-impedance resistor divider to minimize

power consumption in standby. The recommended resistance value is

between 8 MΩ and 16 MΩ. Changing this divider ratio affects the

input current waveform, reduces power factor and increases THD.

A small ceramic capacitor forming an 80 µs time constant must be

connected between the VOLTAGE MONITOR pin and the SIGNAL

GROUND pin to bypass any switching noise present on the rectified

DC bus. This pin also features brown-in/out detection thresholds and

incorporates a weak current source that acts as a pull-down in the

event of an open-circuit condition.

COMPENSATION (C) Pin (Pin 5)

This pin is used for loop pole/zero compensation of the OTA error

amplifier via a network of capacitors and a resistor between the

COMPENSATION pin and SIGNAL GROUND pin.

FEEDBACK (FB) Pin (Pin 6)

This pin is connected to the main voltage regulation feedback resistor

divider network and is also used for fast over and undervoltage

protection. This pin also detects the presence of the feedback

voltage divider network at start-up. The divider ratio should be the

400/3.85 to ensure that nominal PFC output voltage is 400 V.

Positioning a large upper resistor between 8 MΩ and 16 MΩ ±1% is

recommended. A small ceramic capacitor between FEEDBACK and

SIGNAL GROUND, forming a 80 µs time-constant with the bottom

resistor, is required.

POWER GOOD (PG) Pin (Pin 7)

Use of the PG function is optional for PFS517xF. The POWER GOOD

pin is an active low, open-drain connection which sinks current when

the output voltage is in regulation. At start-up, once the FEEDBACK

pin voltage has risen to ~95% of the internal reference voltage, the

POWER GOOD pin is asserted low. After start-up, the output voltage

threshold at which the PG signal becomes high-impedance and

depends on the threshold programmed by the POWER GOOD

THRESHOLD pin resistor. When not used, the POWER GOOD pin

should be left floating.

For PFS527xF this pin is used to implement the boost follower feature.

This is an active low, open-drain connection which sinks current when

the peak detected input voltage is determined to be high-line. Connect

an additional feedback resistor R

BF between BF pin and the FB pin to

change the output voltage between low-line and high-line inputs. This

feature improves efficiency particularly at low-line AC input.

POWER GOOD THRESHOLD (PGT) Pin (Pin 8)

This pin is used to program the output voltage threshold at which the

PG signal becomes high-impedance representing the PFC stage falling

out of regulation. The low threshold for the PG signal is programmed

with a resistor between the POWER GOOD THRESHOLD and SIGNAL

GROUND pins. Tying the POWER GOOD THRESHOLD to the REFERENCE

pin disables the power good function (i.e. POWER GOOD pin remains

high impedance). In boost follower mode, the PGT pin has no

function and should be connected to REFERENCE pin.

POWER SELECTION (PS) Pin (Pin 9)

This pin is used to program the output power of the HiperPFS-5. The

power is programmed with a resistor connected to the SIGNAL

GROUND pin. The power is programmed in 10% steps, between

70% to 100% of nominal power.

VPP Pin (Pin 10)

Must be connected to REF pin.

REFERENCE (R) Pin (Pin 11)

This pin is connected to an external bypass capacitor. The voltage on

this pin is nominally 5 V and is used to supply the control circuitry

inside PFS PowiGaN.

DRIVER VCC DECOUPLING (VDR) Pin (Pin 12)

This pin is connected to an external bypass capacitor. There is an

internal linear regulator which supplies the VDR pin with a regulated

voltage of (5 V nominally). This voltage is used to supply the driver

section of the PFS PowiGaN controller.

BIAS POWER (VCC) Pin (Pin 14)

This is the input for the 6.5-35 VDC bias supply used to power the IC.

The maximum operating voltage must be externally clamped to

prevent the BIAS POWER pin from exceeding 35 VDC.

X CAPACITOR DISCHARGE TERMINAL D1 (Pin 15-16)

Connected together internally to one terminal of the X capacitor.

These two pins are connected together with a bond wire inside

package. For selection of the discharge resistors follow the

recommendations in CAPZero-2 data sheet.

X CAPACITOR DISCHARGE TERMINAL D2 (Pin 18-19)

Connect one pair of pins via a series resistor to each side of the X

capacitor. These two pins are connected together internally with a

bond wire inside package. To select the values for the discharge

resistors follow the recommendations in the CAPZero-2 data sheet.

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