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SSD1339
Rev 1.1
P 21/59 Jul 2005
Solomon Systech
MPU Serial Interface
The serial interface consists of serial clock SCLK, serial data SDIN, D/C#, CS#. In this mode, D0 acts as
SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. D3 to D7, E and R/W pins
can be connected to external ground.
SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C is
sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or
command register in the same clock.
During data writing, an additional NOP command should be inserted before the CS# goes high (Refer to
Figure 7.
Figure 7 –
Display data write procedure in SPI mode
D7
D6
D5
D4
D3
D2
D1
D0
SCLK(D0)
SDIN(D1)
DB1
DB2
DBn
NOP COMMAND
CS#
D/C
SDIN/
SCLK
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