5 V, Slew Rate Limited, Half-Duplex and

Full Duplex RS-485/RS-422 Transceivers

Data Sheet

ADM4850 to ADM4857

Rev. F

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FEATURES

Electronics industries alliance (EIA) RS-485/RS-422 compliant

Data rate options

ADM4850/ADM4854: 115 kbps

ADM4851/ADM4855: 500 kbps

ADM4852/ADM4856: 2.5 Mbps

ADM4853/ADM4857: 10 Mbps

Half-duplex and full duplex options

Reduced slew rates for low electromagnetic interference (EMI)

True fail-safe receiver inputs

5 µA (maximum) supply current in shutdown mode

Up to 256 transceivers on one bus

Outputs high-Z when disabled or powered off

−7 V to +12 V bus common-mode range

Thermal shutdown and short-circuit protection

Pin-compatible with the MAX308x

Specified over the −40°C to +85°C temperature range

Available in 8-lead SOIC, 8-lead LFCSP, and 8-lead MSOP

Qualified for automotive applications

APPLICATIONS

Low power RS-485 applications

EMI sensitive systems

DTE to DCE interfaces

Industrial control

Packet switching

Local area networks

Level translators

GENERAL DESCRIPTION

The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/

ADM4855/ADM4856/ADM4857 are differential line transceivers

suitable for high speed, half-duplex and full duplex data

communication on multipoint bus transmission lines. They

are designed for balanced data transmission and comply with

EIA Standards RS-485 and RS-422. The ADM4850/ADM4851/

ADM4852/ADM4853 are half-duplex transceivers that share

differential lines and have separate enable inputs for the driver

and receiver. The full duplex ADM4854/ADM4855/ADM4856/

ADM4857 transceivers have dedicated differential line driver

outputs and receiver inputs.

The devices have a 1/8-unit load receiver input impedance,

which allows up to 256 transceivers on one bus. Because only one

driver must be enabled at any time, the output of a disabled or

powered down driver is three-stated to avoid overloading the bus.

The receiver inputs have a true fail-safe feature, which ensures a

logic high output level when the inputs are open or shorted.

FUNCTIONAL BLOCK DIAGRAMS

Figure 1. ADM4850/ADM4851/ADM4852/ADM4853 Functional Block Diagram

Figure 2. ADM4854/ADM4855/ADM4856/ADM4857 Functional Block Diagram

This guarantees that the receiver outputs are in a known state

before communication begins and when communication ends.

The driver outputs are slew rate limited to reduce EMI and data

errors caused by reflections from improperly terminated buses.

Excessive power dissipation caused by bus contention or by

output shorting is prevented with a thermal shutdown circuit.

The devices are fully specified over the commercial and industrial

temperature ranges and are available in 8-lead SOIC (ADM4850

through ADM4857), 8-lead LFCSP (ADM4850/ADM4852/

ADM4853), and 8-lead MSOP (ADM4850 only) packages.

Table 1. Selection Table

Device No.

Half-Duplex/Full Duplex

Data Rate

ADM4850

Half

115 kbps

ADM4851

Half

500 kbps

ADM4852

Half

2.5 Mbps

ADM4853

Half

10 Mbps

ADM4854

Full

115 kbps

ADM4855

Full

500 kbps

ADM4856

Full

2.5 Mbps

ADM4857

Full

10 Mbps

RO

RE

R

DE

DI

D

A

B

GND

VCC

ADM4850/ADM4851/

ADM4852/ADM4853

RO

R

A

B

DI

D

Z

Y

GND

VCC

ADM4854/ADM4855/

ADM4856/ADM4857