Quadrant Logic Diagram

and Description

The ATV5000 has: four identical quadrants, 52 identical input/

output logic cells, and 24 identical buried logic cells. The uni-

versal bus routes true and false signals from each of the 52 I/O

pins to all four quadrants. Regional buses route each quadrant’s

flip-flop Q and Q locally. The eight input-only pins are available

in every regional bus.

Each logic cell has a number of "regional" and "universal" prod-

uct terms (see Figure 3). The I/O logic cells (Figures 7, 8, 9)

contain three sum terms, two flip-flops, and an I/O buffer. Sum

term B has five product terms - two universal and three regional.

Sum terms A and C each have four product terms - one universal

and three regional. Flip-flop Q1 has global asynchronous preset,

reset, and clock product terms. Flip-flop Q2 has universal asyn-

chronous reset and clock terms and a regional asynchronous pre-

set term. There is one universal product term for the I/O pin out-

put enable.

The buried logic cells (Figure 4) each contain one flip-flop. The

sum term has one universal product term and four regional prod-

uct terms for a total of five. The flip-flop has universal asynchro-

nous preset, reset, and clock terms. In addition, in each buried

logic cell the sum term can be fed back into the regional bus

instead of the flip-flop. This allows for logic expansion.

Regional product terms have as inputs all quadrant flip-flop out-

puts (or buried flip-flop inputs) and the eight dedicated input

pins. Universal product terms have the same inputs plus the 52

I/O pins and their complements.

Quadrant Clock Pin Assignments

Quadrant

Number

Register

Clock Pin

Latch

Clock Pin

12

1

232

34

336

35

466

68

13 I/O

PINS

REGISTER

CLOCK

LATCH

CLOCK

IN/LIN

Q1

Q2

INPUT/

OUTPUT

LOGIC

CELLS

(13 TOTAL)

REGISTER

CLOCK

16

REGIONAL

BUS

UNIVERSAL

BUS TO ALL

QUADRANTS

Q1/D1

BURIED

LOGIC

CELLS

(6 TOTAL)

OE

UNIVERSAL BUS INPUTS

REGIONAL BUS INPUTS

UNIVERSAL

PRODUCT

TERMS

REGIONAL

PRODUCT

TERMS

ALL 8

INPUT ONLY PINS

Quadrant Structure

Figure 3

16

16

16

16

UNIVERSAL

BUS

REGIONAL

BUS

REGIONAL

BUS

13 I/O CELLS

6 BURIED

LOGIC CELLS

13 I/O CELLS

6 BURIED

LOGIC CELLS

QUADRANT

1

QUADRANT

2

INPUT PINS

1,2,32,34,35,

36,66,68

REGISTER

CLOCK PIN 32

LATCH

CLOCK PIN 34

13 I/O PINS

18,19,21-31

REGISTER

CLOCK PIN 2

LATCH

CLOCK PIN 1

13 I/O PINS

4-15,17

REGIONAL

BUS

REGIONAL

BUS

13 I/O CELLS

6 BURIED

LOGIC CELLS

13 I/O CELLS

6 BURIED

LOGIC CELLS

QUADRANT

4

QUADRANT

3

REGISTER

CLOCK PIN 36

LATCH

CLOCK PIN 35

13 I/O PINS

38-49,51

REGISTER

CLOCK PIN 66

LATCH

CLOCK PIN 68

13 I/O PINS

52,53,55-65

ATV5000 Block Diagram

Figure 2

ATV5000/L

1-195