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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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INA232 датащи(PDF) 22 Page - Texas Instruments |
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INA232 датащи(HTML) 22 Page - Texas Instruments |
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22 / 32 page  Table 7-10. Mask/Enable Register Field Descriptions (continued) Bit Field Type Reset Description 0 LEN (Alert Latch Enable) R/W 0b When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and Alert Function Flag (AFF) bit resets to the idle states when the fault condition has been cleared. When the Alert Latch Enable bit is set to Latch mode, the Alert pin and AFF bit remains active following a fault until this register flag has been read. This bit must be set to use the I2C Alert Response function. 0b = Transparent 1b = Latched Alert pin Return to the Summary Table. 7.6.1.8 Alert Limit Register (Address = 7h) [reset = 0000h] The alert limit register is shown in Table 7-11. Table 7-11. Alert Limit Register Field Descriptions Bit Field Type Reset Description 15-0 LIMIT R/W 0000h The Alert Limit Register contains the value used to compare to the register selected in the Mask/Enable Register to determine if a limit has been exceeded. A two's complement value must be used for the Shunt Over Voltage limit. Limit values entered should match the format of the targeted register Return to the Summary Table. 7.6.1.9 Manufacturer ID Register (Address = 3Eh) [reset = 5449h] The manufacturer ID register is shown in Table 7-12. Table 7-12. MANUFACTURE_ID Register Field Descriptions Bit Field Type Reset Description 15-0 MANUFACTURE_ID R 5449h Reads back TI in ASCII Return to the Summary Table. INA232 SBOSAA2 – DECEMBER 2022 www.ti.com 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 |
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