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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AS1744 датащи(PDF) 8 Page - ams AG |
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AS1744 датащи(HTML) 8 Page - ams AG |
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8 / 16 page  AS1744, AS1745 austriamicrosystems Data Sheet Timing Diagrams and Test Setups www.austriamicrosystems.com Revision 1.53 8 - 16 Timing Diagrams and Test Setups Figure 11. Switching Time Figure 12. Break-Before-Make Interval Figure 13. Charge Injection AS1744/ AS1745 COMx RLOAD VOUT INx V+ V+ Switch Output Logic Input 0 0 VOUT VIH + 0.5V tON tOFF tR < 5ns tF < 5ns 50% 50% 0.9 x VOUT NOx or NCx VIN NCx or NOx CLOAD † † Includes stray capacitance and fixture capacitance. 0.9 x VOUT Logic input waveforms inverted for switches that have the opposite logic sense. GND Logic Input AS1744/ AS1745 COMx VOUT INx V+ V+ NOx or NCx VIN NCx or NOx † Includes stray capacitance and fixture capacitance. Logic Input 0 VOUT VIH + 0.5V tD tR < 5ns tF < 5ns 50% 0.9 x VOUT RLOAD CLOAD † GND Logic Input AS1744/ AS1745 COMx NCx or NOx CLOAD VOUT RGEN V+ VOUT INx ∆VOUT INx depends on switch configuration; input polar- ity is determined by the sense of the switches. Q = ∆VOUT x CLOAD V+ VINL to VINH INx INx Off Off Off Off On On VGEN GND |
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