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AS1150, AS1151

Data Sheet

LVDS Interface

8 Detailed Description

The AS1150 and AS1151 are 500Mbps, four-channel LVDS receivers intended for high-speed, point-to-point, low-

power applications. Each independent channel accepts and converts an LVDS input to an LVTTL/LVCMOS output.

The devices are capable of detecting differential signals from 100mV to 1V within an input voltage range of 0 to 2.4V.

The 250 to 450mV differential output of an LVDS driver is nominally centered around 1.25V. Due to the receiver input

voltage range, a ±1V voltage shift in the signal relative to the receiver is allowed. Thus, a difference in ground refer-

ences of the transmitter and the receiver, as well as the common mode effect of coupled noise, can be tolerated.

LVDS Interface

The LVDS Interface Standard is a signaling method defined for point-to-point communication over a controlled-imped-

ance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower volt-

age swing than other common communication standards, resulting in higher data rates, reduced power consumption

and EMI emissions, and less susceptibility to noise.

The devices fully comply with the LVDS standard input voltage range of 0 to +2.4V referenced to receiver ground.

The AS1151 has an integrated termination resistors connected internally across each receiver input. This internal ter-

mination saves board space, eases layout, and reduces stub length compared to an external termination resistor. In

other words, the transmission line is terminated on the IC.

Failsafe Circuit

The devices contain an integrated failsafe circuit to prevent noise at inputs that are open, undriven and terminated, or

undriven and shorted.

Open or undriven terminated input conditions can occur if there is a cable failure or when the LVDS driver outputs are

high impedance. A short condition also can occur because of a cable failure. The failsafe circuit of the AS1150/AS1151

automatically sets the output high if any of these conditions are true.

0.3V and the failsafe circuit is not activated. If the inputs are open, undriven and shorted, or undriven and parallel ter-

activating the failsafe circuit and thus forcing the device output high.

Figure 16. Failsafe Input Circuit

AS1151

AS1150

INx-

OUTx

INx+

INx-

OUTx

INx+