8.2.2 Detailed Design Procedure

The ESD1LIN24-Q1, ESD751-Q1, and ESD761-Q1 have a VRWM of ±24 V to protect the diode from being

damaged during a short to battery event that can occur by reversing the terminal connections during jumpstart.

The bidirectional characteristic ensures both positive and negative polarity are protected. The low capacitance of

5 pF or less permits data rates up to 10 Mbps, which allows the designer to meet the requirements for LIN. The 1

kΩ and VSUP diode allows the LIN signal to be pulled up to a diode drop below the battery voltage.

8.2.3 Application Curves

Figure 8-2. +8-kV Clamped IEC Waveform

Figure 8-3. −8-kV Clamped IEC Waveform

9 Power Supply Recommendations

This device is a passive TVS diode-based ESD protection device, therefore there is no requirement to power it.

Ensure that the maximum voltage specifications for each pin is not violated.

10 Layout

10.1 Layout Guidelines

• The optimum placement is as close to the connector as possible.

– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,

resulting in early system failures.

– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away

from the protected traces which are between the TVS and the connector.

• Route the protected traces as straight as possible.

• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded

corners with the largest radii possible.

– Electric fields tend to build up on corners, increasing EMI coupling.

• If pin 1 or 2 is connected to ground, use a thick and short trace for this return path.

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ESD1LIN24-Q1, ESD751-Q1, ESD761-Q1

SLVSGS4C – SEPTEMBER 2022 – REVISED DECEMBER 2022

Copyright © 2022 Texas Instruments Incorporated

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Product Folder Links: ESD1LIN24-Q1 ESD751-Q1 ESD761-Q1