APL5913 datasheet(14/19 Pages) ANPEC

14 / 19 page

Rev. A.4 - May., 2005

APL5913

www.anpec.com.tw

Feedback Network (Cont.)

Application Information (Cont.)

Select a proper R1(selected) to be a little larger

than the calculated R1.

- Calculate the C1 as the following :

Where R1=R1(selected)

Select a proper C1(selected) to be a little smaller

than the calculated C1.

- The C1 calculated from equation (4) must meet

the following equation:

Where R1=R1(calculated) from equation (3)

If the C1(calculated) can not meet the equation

(5), please use the Condition 3.

- Use equation (2) to calculate the R2.

•Condition 3 : Low ESR (eg. Ceramic Capacitors)

- Calculate the R1 as the following:

Select a proper R1(selected) to be a little larger

than the calculated R1. The minimum selected

R1 is equal to 1k

Ω when the calculated R1 is

smaller than 1k or negative.

- Calculate the C1 as the following :

Where R1=R1(selected)

Select a proper C1(selected) to be a little smaller

than the calculated C1.

- The C1 calculated from equation (7) must meet

the following equation :

Where R1=R1(calculated) from equation (6)

If the C1(calculated) can not meet the equation (8),

please use the Condition 2.

- Use equation (2) to calculate the R2.

The reason to have three conditions described above

is to optimize the load transient responses for all kinds

of the output capacitor. For stability only, the Condition

2, regardless of equation (5), is enough for all kinds of

output capacitor.

[

]

(4)

........

101

ESR

0.71

)

OUT(uF)

)

(pF)

Ω

⋅

(5)

37.5

ESR

143

7.2

)

OUT(V)

)

(pF)









⋅







 +

⋅

≥

Ω

(6)

37.5

300)

ESR

(2.1

OUT(V)

OUT(uF)

)

⋅

−

⋅

Ω

(7)

37.5

34.2)

ESR

(0.24

)

OUT(V)

OUT(uF)

)

(pF)









⋅

Ω

(8)

ESR

1.25

0.033

OUT(uF)

)

OUT(V)

(pF)

⋅









⋅

≥

Ω

PCB Layout Considerations (See Figure 2)

1. Please solder the Exposed Pad and VIN together

on the PCB. The main current flow is through the

exposed pad. Refer Figure 3 to make a proximate

topology.

2. Please place the input capacitors for VIN and

VCNTL pins near pins as close as possible.

3. Ceramic decoupling capacitors for load must be

placed near the load as close as possible.

4. To place APL5913 and output capacitors near the

load is good for performance.

5. The negative pins of the input and output capaci-

tors and the GND pin of the APL5913 are connected

to the ground plane of the load.

6. Please connect PIN 3 and 4 together by a wide

track.

7. Large current paths must have wide tracks.

8. See the Typical Application

(see next page Figure 2)

- Connect the one pin of the R2 to the GND of

APL5913

- Connect the one pin of R1 to the Pin 3 of APL5913

- Connect the one pin of C1 to the Pin 3 of APL5913

APL5913 датащи(PDF) 14 Page - Anpec Electronics Coropration

APL5913 датащи(HTML) 14 Page - Anpec Electronics Coropration

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

датащи скачать

ссылки URL