Functional Description

A functional diagram of the MM58201 LCD driver is shown

in

Figure 1 Connection diagrams are shown in Figure 2

SERIAL INPUTS AND OUTPUTS

A negative-going edge on the CS input initiates a frame The

CS input must then stay low for at least one rising edge of

CLK IN and may not be pulsed low again for the next 31

clocks At least one clock must occur while CS is high If

CLK IN is held at a logic ‘‘1’’ CS is disabled This allows the

signal that drives CS to be used for other purposes when

the MM58201 is not being addressed

CLK IN latches data from the DATA IN input on its rising

edge Data from the DATA OUT pin changes on the falling

edge of CLK IN and is valid before the next rising edge

The first five bits of data following CS are the address bits

(Figure 3) The address selects the column where the oper-

ation is to start Bit 1 is the MSB and bit 5 is the LSB The

sixth bit is the readwrite bit A logic ‘‘1’’ specifies a read

operation and a logic ‘‘0’’ specifies a write operation The

next 24 bits are the data bits The first data bit corresponds

to the BP1 row of the display the second data bit to the BP2

row and so on After the eighth and sixteenth data bits the

column pointer is incremented

When starting address

10110 or 10111 is specified the column pointer increments

from 10111 to 00000

During a read or write cycle the LCD segment outputs do

not reflect the data in the RAM To avoid disrupting the

pattern viewed on the display the read or write cycle time

should be kept short Since the LCD turn-on time can be as

little as 30 ms a clock rate of at least 10 kHz would be

required in order to address the entire contents of the RAM

within that time interval The formula below can be used to

estimate the minimum clock rate

30

time of the LCD as specified by the LCD manufacturer

The DATA OUT output is an open drain N-channel device to

allows the controller to operate at a lower supply voltage

and also permits the DATA OUT output to be wired in paral-

lel with the DATA OUT outputs from any other drivers in the

system

To program the number of backplanes being driven and the

MS bit load address 11000 a write bit three bits for the

number of backplanes (Table I) and the MS bit The re-

maining 20 data bits will be ignored but it is necessary to

provide 21 more clocks before initiating another frame

TABLE I Backplane Select

Number of

B2

B1

B0

Backplanes

2

001

3

010

4

011

5

100

6

101

7

110

8

111

RC OSC Pin

This oscillator generates the timing required for multiplexing

the liquid crystal display The oscillator operates at a fre-

quency that is 4h times the refresh rate of the display

where h is the number of backplanes programmed Since

the refresh rate should be in the range from 32 Hz to 100

Hz the oscillator frequency must be

The frequency of oscillation is related to the external R and

C components in the following way

1

125 RC

g

30%

The value used for the external resistor should be in the

range from 10 kX to1MX

The value used for the external capacitor should be less

than 0005 mF

the segments on the LCD If eight backplanes are being

The voltage for optimum contrast will vary from display to

display It also has a significant negative temperature coeffi-

cient

from 10 kX to 30 kX A suitable circuit is shown in

Figure 5

reduces the supply current to less than 300 mA per driver

BACKPLANE AND SEGMENT OUTPUTS

Connect the backplane and segment outputs directly to the

LCD row and column lines The outputs are designed to

drive a display with a total ON capacitance of up to 2000 pF

The output structure consists of transmission gates tapped

A critical factor in the lifetime of an LCD is the amount of DC

offset between a backplane and segment signal Typically

50 mV of offset is acceptable The MM58201 guarantees an

offset of less than 10 mV

The BP1 output is disabled when the MS bit is set to zero

This allows the BP1 output from the master chip to be con-

nected directly to it so that synchronizing signals can be

generated Synchronization occurs once each refresh cycle

so the cascaded chips are assured of remaining synchroniz-

ed

4