APR349

Document number: DS43554 Rev. 2 - 2

5 of 10

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July 2021

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APR349

Operation Description

VDD Regulator and UVLO Protection

The VDD is supplied by the PLR (Pulse Linear Regulator) from the drain voltage, or LDO from the VOUT voltage. When the APR349 operates at a

low voltage output condition, a Pulse Linear Regulator is integrated in the controller to provide voltage to the VDD pin, in which the system output

voltage may drop to 2V. Meanwhile, when the system output voltage is higher than 4.75V, the VDD bias voltage generating circuit will change from

the PLR to the LDO circuit.

When the VDD provides bias voltage for the controller, a capacitor (typical 3.3μF) should be connected between the VDD pin and GND pin. The

APR349 also has UVLO protection. When VDD drops below VDD_UVLO, the IC will stop providing gate drive pulse.

GATE Turn-On Logic

The APR349 determines the synchronous rectification MOSFET turn-on moment by monitoring the MOSFET drain-to-source voltage. When the

drain voltage is lower than the turn-on threshold voltage VON_TH, the IC outputs a positive drive voltage after a turn-on delay time (tD_ON). The

MOSFET will turn on and the current will transfer from the body diode into the MOSFET’s channel.

Moreover, the device also sets an internally fixed, volt-sec product threshold to prevent false turn-on within ringing voltage cycle. Regarding the

sensed voltage of the DRAIN pin, the volt-second product above the VCC voltage at the primary switch on-time is much higher than the volt-

second product of ringing voltage above VCC. Therefore, the APR349 can turn on the synchronous rectifier depending on the detected volt-

second product of drain voltage above VCC. The APR349 has an internal parameter Kqs, which multiplies Rx resistor value to generate volt-

second product threshold. Thus, changing the Rx resistor can adjust the volt-second product threshold.

A

rea2 = Rx ∗ Kqs

In general, the Area1 and Area3 values depend on system design. Area2 should be set in the middle of Area1 and Area3 to ensure suitable

design margins.

Area3 < ������������ ∗ ������������������ < ������������������������1

VDET

VCC

Area3

Area1=(VDRAIN-VOUT)*tONP

Area2=Kqs*Rx

Figure 1. Volt-Second Product Function