5 Pin Configuration and Functions

1

VDD

10

VREF

2

VOUTA

9

VOUTB

3

RSTSEL

8

SDIN

4

AGND

7

SYNC

5

RESET

6

SCLK

Not to scale

Figure 5-1. DRX (10-Pin WSON) Package, Top View

Table 5-1. Pin Functions

PIN

TYPE

DESCRIPTION

NAME

NO.

AGND

4

Ground

Ground reference point for all circuitry on the device.

RESET

5

Input

Asynchronous reset. Active low. If RESET is low, all DAC channels reset either to zero-scale

(RSTSEL = AGND) or to midscale (RSTSEL = VDD).

RSTSEL

3

Input

Reset select pin.

DACs power up to zero scale if RSTSEL = AGND.

DACs power up to midscale if RSTSEL = VDD.

SCLK

6

Input

Serial interface clock of SPI.

SDIN

8

Input

Serial interface data input of SPI. Data are clocked into the input shift register on each falling edge

of the SCLK pin.

SYNC

7

Input

Serial data enable of SPI. Active low. This input is the frame-synchronization signal for the serial

data. When the signal goes low, the serial interface input shift register is enabled.

VDD

1

Power

Analog supply voltage (2.7 V to 5.5 V)

VOUTA

2

Output

Analog output voltage from DAC A

VOUTB

9

Output

Analog output voltage from DAC B

VREF

10

Input

This pin is the external reference input to the device.

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DAC82002

SBASAK1A – AUGUST 2022 – REVISED DECEMBER 2022

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