ISL78840ASxH, ISL78841ASxH, ISL78843ASxH, ISL78845ASxH, ISL738840ASEH, ISL738841ASEH, ISL738843ASEH, ISL738845ASEH

FN7952 Rev.4.00

Page 13 of 18

Feb 25, 2020

Adding slope compensation is accomplished in the

ISL7884xASxH and ISL73884xASEH devices using an external

buffer transistor and the RTCT signal. A typical application sums

the buffered RTCT signal with the current sense feedback and

applies the result to the CS pin as shown in Figure 9.

Assuming the designer has selected values for the RC filter (R6

and C4) placed on the CS pin, the value of R9 required to add the

appropriate external ramp can be found by superposition.

The factor of 2.05 in Equation 16 arises from the peak amplitude

of the sawtooth waveform on RTCT minus a base-emitter junction

drop. That voltage multiplied by the maximum duty cycle is the

voltage source for the slope compensation. Rearranging to solve

for R9 yields Equation 17:

The value of RCS determined in Equation 15 must be rescaled so

that the current sense signal presented at the CS pin is that

predicted by Equation 13. The divider created by R6 and R9

makes this necessary.

Example:

VIN = 12V

VO = 48V

Ls = 800µH

Ns/Np = 10

Lp = 8.0µH

IO = 200mA

Switching Frequency, fSW = 200kHz

Duty Cycle, D = 28.6%

R6 = 499Ω

Solve for the current sense resistor, RCS, using Equation 15.

RCS = 295mΩ

Determine the amount of voltage, Ve, that must be added to the

current feedback signal using Equation 12.

Ve = 92.4mV

Using Equation 17, solve for the summing resistor, R9, from CT to

CS.

R9 = 2.67kΩ

Determine the new value of RCS (R’CS) using Equation 18.

R’CS = 350mΩ

Additional slope compensation may be considered for design

margin. The previous discussion determines the minimum

external ramp that is required. The buffer transistor used to

create the external ramp from RTCT should have a sufficiently

high gain (>200) so as to minimize the required base current.

Whatever base current is required reduces the charging current

into RTCT and will reduce the oscillator frequency.

Fault Conditions

A Fault condition occurs if VREF falls below 4.65V. When a Fault

is detected, OUT is disabled. When VREF exceeds 4.80V, the Fault

condition clears and OUT is enabled.

Ground Plane Requirements

Careful layout is essential for satisfactory operation of the device.

A good ground plane must be employed. A unique section of the

ground plane must be designated for high di/dt currents

associated with the output stage. VDD should be bypassed

directly to GND with good high frequency capacitors.

References

[1] Ridley, R., “A New Continuous-Time Model for Current Mode

Control”, IEEE Transactions on Power Electronics, Vol. 6,

No. 2, April 1991.

CS

RTCT

R6

C4

R9

VREF

FIGURE 9. SLOPE COMPENSATION

Ve

2.05D R6



R6 R9

+

----------------------------

=

V

(EQ. 16)

R9

2.05D Ve

–

 R

6



Ve

----------------------------------------------

=



(EQ. 17)

R



CS

R6 R9

+

R9

--------------------- RCS



=

(EQ. 18)