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DF2S5.1ASL датащи(PDF) 2 Page - Toshiba Semiconductor

номер детали DF2S5.1ASL
подробное описание детали  ESD Protection Diodes Silicon Epitaxial Planar
PDF  8 Pages
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производитель  TOSHIBA [Toshiba Semiconductor]
домашняя страница  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

DF2S5.1ASL датащи(HTML) 2 Page - Toshiba Semiconductor

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DF2S5.1ASL
2
4.
4.
4.
4. Electrical Characteristics (Unless otherwise specified, T
Electrical Characteristics (Unless otherwise specified, T
Electrical Characteristics (Unless otherwise specified, T
Electrical Characteristics (Unless otherwise specified, Taaaa = 25
= 25
= 25
= 25
))))
VRWM: Working peak reverse
voltage
VZ: Zener voltage
VBR: Reverse breakdown voltage
ZZ: Dynamic impedance
IZ: Zener current
IBR: Reverse breakdown current
IR: Reverse current
VC: Clamp voltage
IPP: Peak pulse current
RDYN: Dynamic resistance
IF: Forward current
VF: Forward voltage
Fig.
Fig.
Fig.
Fig. 4.1
4.1
4.1
4.1 Definitions of Electrical Characteristics
Definitions of Electrical Characteristics
Definitions of Electrical Characteristics
Definitions of Electrical Characteristics
Characteristics
Working peak reverse voltage
Zener voltage
(Reverse breakdown voltage)
Dynamic impedance
Reverse current
Clamp voltage
Clamp voltage
Dynamic resistance
Total capacitance
Symbol
VRWM
VZ
(VBR)
ZZ
IR
VC
VC
RDYN
Ct
Note
(Note 1)
(Note 2)
(Note 2)
(Note 3)
Test Condition
IZ = 5 mA
(IBR = 5 mA)
IZ = 5 mA
(IBR = 5 mA)
VRWM = 1.5 V
IPP = 1 A
IPP = 2.5 A
ITLP = 16 A
ITLP = 30 A
VR = 0 V, f = 1 MHz
Min
4.8
Typ.
5.1
5.5
6.5
10
13
0.2
45
Max
1.5
5.4
70
1
12
Unit
V
V
µA
V
V
pF
Note 1: Based on IEC61000-4-5 8/20 µs pulse.
Note 2: TLP parameter: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns,
extraction of dynamic resistance using a least-squares fit of TLP characteristics at IPP between 8 A to 16 A.
Note 3: Guaranteed by design.
2015-12-11
Rev.1.0
©2015 Toshiba Corporation



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