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MFS5600AMMA8ES датащи(PDF) 28 Page - NXP Semiconductors

номер детали MFS5600AMMA8ES
подробное описание детали  Automotive buck regulator and controller with voltage monitors and watchdog timer
PDF  111 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

MFS5600AMMA8ES датащи(HTML) 28 Page - NXP Semiconductors

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NXP Semiconductors
FS5600
Automotive buck regulator and controller with voltage monitors and watchdog timer
OTP_SW2_SLOPECOMP[5:0]
SW2 slope compensation (mV/µs)
110100
938
110101
958
110110
979
110111
999
111000
1020
111001
1041
111010
1061
111011
1082
111100
1103
111101
1124
111110
1124
111111
1144
Table 26. OTP_SW2_SLOPECOMP[5:0] selection...continued
12.2.8 SW2 fault monitoring
SW2FB pin voltage is compared against an internal reference to detect overvoltage and
undervoltage faults in SW2. See Table 18 for monitoring thresholds.
When OTP_SW2_OV_PGOOD1 = 1, an overvoltage fault on SW2 asserts PGOOD1.
Similarly, when OTP_SW2_OV_PGOOD2 = 1, an overvoltage fault on SW2 asserts
PGOOD2.
When OTP_SW2_UV_PGOOD1 = 1, an undervoltage fault on SW2 asserts PGOOD1.
Similarly, when OTP_SW2_UV_PGOOD2 = 1, an undervoltage fault on SW2 asserts
PGOOD2.
The SW2_UV_I and SW2_OV_I bits are latched to 1 respectively if undervoltage and
overvoltage faults are detected. The latch bits can be cleared by writing a 1 to them.
SW2_UV_RT and SW2_OV_RT read-only bits indicate the real-time status of the faults.
13 BIAS_IN Input
An external voltage between 3.7 V and 5.5 V can be applied at the BIAS_IN pin to reduce
power consumption in the FS5600. When a valid voltage at BIAS_IN is detected, VCC
is powered directly from the BIAS_IN path, eliminating the power dissipation in the high-
voltage LDO from VIN to VCC.
In the application, if either SW1 or SW2 is set to 5.0 V on the output, NXP recommends
connecting that output to BIAS_IN. If an external 5 V is available in the system, that may
be connected to BIAS_IN. Ensure that the BIAS_IN voltage does not exceed 5.5 V.
14 FS5600 Clock Management
The clock management system provides a top-level management control scheme of
internal clock and external synchronization intended to be used primarily for the switching
regulators. The clock management system incorporates various sub-blocks:
FS5600
All information provided in this document is subject to legal disclaimers.
© 2022 NXP B.V. All rights reserved.
Product data sheet
Rev. 3 — 2 August 2022
28 / 111



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