AM486DX2 datasheet(43/67 Pages) AMD

43 / 67 page

Am5X86 Microprocessor

AMD

PRELIMINARY

7.3.4

SMRAM State Save Map

When SMI is recognized on an instruction boundary, the

CPU core first sets the SMIACT signal Low, indicating

to the system logic that accesses are now being made

to the system-defined SMRAM areas. The CPU then

writes its state to the state save area in the SMRAM.

The state save area starts at SMBASE + [8000h +

7FFFh]. The default CS Base is 30000h; therefore, the

default state save area is at 3FFFFh. In this case, the

CS Base is also referred to as the SMBASE.

Table 10. SMRAM State Save Map

Offset*

Writable?

7FFCh

CRO

7FF8h

CR3

7FF4h

EFLAGS

Yes

7FF0h

EIP

Yes

7FECh

EDI

Yes

7FE8h

ESI

Yes

7FE4h

EBP

Yes

7FE0h

ESP

Yes

7FDCh

EBX

Yes

7FD8h

EDX

Yes

7FD4h

ECX

Yes

7FD0h

EAX

Yes

7FCCh

DR6

7FC8h

DR7

7FC4h

TR*

7FC0h

LDTR*

7FBCh

GS*

7FB8h

FS*

7FB4h

DS*

7FB0h

SS*

7FACh

CS*

7FA8h

ES*

7FA7h–7F98h Reserved

7F94h

IDT Base

7F93h–7F8Ch Reserved

7F88h

GDT Base

7F87h–7F08h Reserved

7F04h

I/O Trap Word

7F02h

Halt Auto Restart

Yes

7F00h

I/O Trap Restart

Yes

7EFCh

SMM Revision Identifier

Yes

7EF8h

State Dump Base

Yes

7EF7h–7E00h Reserved

Note:

*Upper 2 bytes are not modified.

If the SMBASE relocation feature is enabled, the SM-

RAM addresses can change. The following formula is

used to determine the relocated addresses where the

context is saved: SMBASE + [8000h + Register Offset],

where the default initial SMBASE is 30000h and the

are for new registers in future CPUs. Some registers in

the SMRAM state save area may be read and changed

by the SMI handler, with the changed values restored

to the processor register by the RSM instruction. Some

(Modifying these registers results in unpredictable be-

havior.) The values stored in the “reserved” areas may

change in future CPUs. An SMI handler should not rely

on values stored in a reserved area.

The following registers are written out during SMSAVE

mode to the RESERVED memory locations (7FA7h–

7F98h, 7F93h–7F8Ch, and 7F87h–7F08h), but are not

visible to the system software programmer:

s DR3–DR0

s CR2

s CS, DS, ES, FS, GS, and SS hidden descriptor

registers

s EIP_Previous

s GDT Attributes and Limits

s IDT Attributes and Limits

s LDT Attributes, Base, and Limits

s TSS Attributes, Base, and Limits

If an SMI request is issued to power down the CPU, the

values of all reserved locations in the SMM state save

area must be saved to non-volatile memory.

The following registers are not automatically saved and

restored by SMI and RSM:

s TR7–TR3

s FPU registers:

—STn

—FCS

—FSW

—Tag Word

— FP instruction pointer

— FP opcode

— Operand pointer

Note: You can save the FPU state by using an FSAVE

or FNSAVE instruction.

For all SMI requests except for power down suspend/

resume, these registers do not have to be saved be-

cause their contents will not change. During a power

down suspend/resume, however, a resume reset clears

these registers back to their default values. In this case,

the suspend SMI handler should read these registers

directly to save them and restore them during the power

up resume. Anytime the SMI handler changes these

registers in the CPU, it must also save and restore them.

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