Figure 16. Digital Inrush Current Limiter function with a semi-controlled input bridge

VAC

T1

T2

L

STNRGPF12 has embedded this technique, and it drives T1 and T2 alternately according the polarity of the

mains and applying a short ON time. To reduce the inrush current the switches are triggered at the end of the line

voltage. In this way the output capacitors initially are charged at low voltage and after it will increase smoothly

allowing also a better control of the Inrush current.

Figure 17. Digital Inrush Current Limiter function: sequence of driving of the SCR

t

vAC

T

T1

T2

T

T

T

T

T

TOFF - TON

TON

2TON

TOFF

TOFF - 2TON

TOFF-3TON

3TON

4TON

DC Bus

In order to charge the output capacitors up to the peak voltage of AC mains, the switches T1 and T2 must be

triggered on the following cycle with TON phase shift respect the previous one. (See Figure 17). If this Step

Phase Shift is very short (few microseconds) from half cycle to half cycle, thanks to the presence of the PFC

inductors, the capacitors will be charged maintaining low the line current. Usually this delay is constant, and we

call this technique “Constant Progressive Step Phase Control”.

3.7.2

PFC Soft Power-ON

After the inrush current limiter phase the device will performs the Soft Power-On phase. The current reference will

generate a constant reference signal and both PWM0 and PWM1 channels will be activated. In this phase the

PFC output voltage will increase up to the setpoint (Vout_ref).

As soon as the PFC Soft Power ON procedure is completed and the voltage reaches the setpoint Vout_ref (See

Figure 18) the device performs the following operations:

•

The PFC_OK pin is pulled low. When this pin is low indicates that the PFC is ready for load connection on

the output.

STNRGPF02, STNRGPF12

Start-up & Inrush Current Limiter function

DS12895 - Rev 2

page 15/43