LM5032 datasheet(11/22 Pages) NSC

11 / 22 page

Functional Description

The LM5032 contains all the features necessary to imple-

ment two independently regulated current mode dc/dc con-

verters, or a single high current converter comprised of two

parallel interleaved channels using the Forward converter

topology. The two controllers operate 180˚ out of phase from

a common oscillator, thereby reducing input ripple current.

Each regulator channel contains a complete PWM controller,

current sense input, soft-start circuit, and gate driver output.

Common to both channels are the startup and V

CC regulator,

line under-voltage lockout, 2 MHz capable oscillator, maxi-

mum duty cycle control, and the hiccup mode fault protection

circuit.

The gate driver outputs (OUT1, OUT2) are designed to drive

N-channel MOSFETs. Their compound configuration re-

duces the turn-off-time, thereby reducing switching losses.

Additional features include thermal shutdown, slope com-

pensation, and the oscillator synchronization capability.

Line Under-Voltage Lock Out,

UVLO, Shutdown

The LM5032 contains a line under-voltage lockout circuit

(UVLO) designed to enable the V

CC regulator and output

drivers when the system voltage (V

PWR) exceeds the de-

sired level (see Figure 15). V

PWR is the voltage normally

applied to the transformer primary, and usually connected to

the VIN pin (see the schematic on Page 1). The threshold at

the UVLO comparator is 1.25V. An external resistor divider

connected from V

PWR to ground provides 1.25V at the UVLO

pin when V

PWR is increased to the desired turn-on threshold.

When V

PWR is below the threshold the VCC regulator and

output drivers are disabled, and the internal 20 µA current

source is off. When V

PWR reaches the threshold, the com-

parator output switches low to enable the internal circuits

and the 20 µA current source. The 20 µA flows into the

external divider’s junction, raising the voltage at UVLO,

thereby providing hysteresis. Internally the voltage at UVLO

also drives the Maximum Duty Cycle Limiter circuit (de-

scribed below), which may influence the values chosen for

the UVLO pin resistors. At maximum V

PWR, the voltage at

UVLO should not exceed 6V. Refer to the Applications Infor-

mation section for a procedure to calculate the resistors

values.

The LM5032 controller can be shutdown by forcing the

UVLO pin below 1.25V with an external switch. When the

UVLO pin is low, the outputs and the V

CC regulator are

disabled, and the LM5032 enters a low power mode. If VCC

pin is not powered from an external source, the current into

VIN drops to a nominal 500 µA. If the VCC pin is powered

from an external source, the current into VIN is nominally 50

µA, and the current into the VCC pin is approximately 4.3

mA. To disable one regulator without affecting the other, see

the description of the Soft-start section.

Startup Regulator, VIN, VCC

The high voltage startup regulator is integral to the LM5032.

The input pin VIN can be connected directly to a voltage

between 13V and 100V, with transient capability to 105V.

The startup regulator provides bias voltages to the series

pass V

CC regulator and the UVLO circuit. The VCC regulator

is disabled until the voltage at the UVLO pin (described

above) exceeds 1.25V. For applications where V

PWR ex-

ceeds 100V the internal startup regulator can be powered

from an external startup regulator or other available low

voltage source. See the Applications Information section for

details.

The V

CC under-voltage threshold circuit (UVT) monitors the

VCC regulator output. When the series pass regulator is

enabled and the internal V

CC voltage increases to > 7.6V,

the UVT comparator activates the PWM controller and out-

put drivers via the Drivers Off signal. The UVT comparator

has built-in hysteresis, with the lower threshold nominally set

to 6.2V. See Figure 2 and Figure 15.

When enabled, the V

CC regulated output is 7.7V ±4% with

current limited to a minimum of 19 mA (typically 22 mA). The

regulator’s output impedance is ) 6

Ω.

The VCC pin requires a capacitor to ground for stability, as

well as to provide the surge currents to the external MOS-

FETs via the gate driver outputs. The capacitor should be

physically close to the VCC and GND pins.

In most applications it is necessary to power V

CC from an

external source as the average current required at the output

drivers may exceed the current capability of the internal

regulator and/or the thermal capability of the LM5032 pack-

age (see Figure 5). Normally the external source is derived

from the converter’s power stage once the LM5032 outputs

are active. Refer to the Applications Information section for

more information.

Drivers Off, V

CC Disable

Referring to Figure 15, Drivers Off and V

CC Disable are

internal signals which, when active disable portions of the

LM5032. If the UVLO pin is below 1.25V, or if the thermal

shutdown activates, the V

CC Disable line switches high to

disable the V

CC regulator. UVLO also activates the Drivers

Off signal to disable the output drivers, connect the SS1,

SS2, COMP1, COMP2 and RES pins to ground, and enable

the 50 µA Soft-start current sources.

If the V

CC voltage falls below the under-voltage threshold of

6.2V , the UVT comparator activates only the Drivers Off

signal. The output drivers are disabled but the V

CC regulator

is not disabled. Additionally, the CS1, CS2, SS1, SS2,

COMP1, COMP2 and RES pins are internally grounded, and

the 50 µA Soft-start current sources are enabled.

Oscillator

The oscillator frequency is set with an external resistor R

connected between the RT/SYNC and GND1 pins. The re-

sistor value is calculated from:

(1)

where F

S is the desired oscillator frequency in kHz (maxi-

mum of 2 MHz), and R

T is in k

Ω. See Figure 8. The two gate

driver outputs (OUT1 and OUT2) switch at half the oscillator

frequency and 180˚ out of phase with each other. The volt-

20135020

FIGURE 15. Drivers Off and V

CC Disable

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