Applications information

STGIPL14K60, STGIPL14K60-S

18/26

DocID15589 Rev 11

5.1

Recommendations

•

Input signal HIN is active high logic. A 85k

Ω (typ.) pull down resistor is built-in for each

high side input. If an external RC filter is used, for noise immunity, pay attention to the

variation of the input signal level.

•

Input signal LIN is active low logic. A 720 k

Ω (typ.) pull-up resistor, connected to an

internal 5 V regulator through a diode, is built-in for each low side input.

•

To prevent the input signals oscillation, the wiring of each input should be as short as

possible.

•

By integrating an application specific type HVIC inside the module, direct coupling to

MCU terminals without any opto-coupler is possible.

•

Each capacitor should be located as nearby the pins of IPM as possible.

•

Low inductance shunt resistors should be used for phase leg current sensing.

•

Electrolytic bus capacitors should be mounted as close to the module bus terminals as

possible. Additional high frequency ceramic capacitor mounted close to the module

pins will further improve performance.

•

The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see

Section 4: Smart shutdown function for detailed info).

Note:

For further details refer to AN3338.

Table 15. Recommended operating conditions

Symbol

Parameter

Conditions

Value

Unit

Min.

Typ.

Max.

VPN

Supply Voltage

Applied between P-Nu, Nv, Nw

300

400

V

VCC

Control supply voltage

Applied between VCC-GND

13.5

15

18

V

VBS

High side bias voltage

Applied between VBOOTi-OUTi for

i = U, V, W

13

18

V

tdead

Blanking time to

prevent Arm-short

For each input signal

1

µs

fPWM

PWM input signal

-40°C < Tc < 100°C

-40°C < Tj < 125°C

20

kHz

TC

Case operation

temperature

100

°C