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ICS94241 датащи(PDF) 6 Page - Integrated Circuit Systems

номер детали ICS94241
подробное описание детали  Programmable TCH??for Differential PIII??Processor
PDF  16 Pages
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производитель  ICST [Integrated Circuit Systems]
домашняя страница  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS94241 датащи(HTML) 6 Page - Integrated Circuit Systems

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6
ICS94241
0453C—10/26/04
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
X
#
2
S
F
d
e
h
c
t
a
L
6
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B0
41
0
M
A
R
D
S
2
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B3
41
0
K
L
C
U
P
C
0
t
i
B4
41
S
C
_
K
L
C
U
P
C
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B6
1
0
K
L
C
I
C
P
5
t
i
B3
11
6
K
L
C
I
C
P
4
t
i
B2
11
5
K
L
C
I
C
P
3
t
i
B1
11
4
K
L
C
I
C
P
2
t
i
B0
11
3
K
L
C
I
C
P
1
t
i
B9
1
2
K
L
C
I
C
P
0
t
i
B7
1
1
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B-
X
#
1
S
F
d
e
h
c
t
a
L
2
t
i
B-
X
#
4
S
F
d
e
h
c
t
a
L
1
t
i
B-
X
#
3
S
F
d
e
h
c
t
a
L
0
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B6
41
1
F
E
R
0
t
i
B7
41
0
F
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B-
X
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B-
X
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B-
X
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B-
X
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B-
X
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B-
X
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: This is an unused register writing to this register
will not affect device performance or functinality.
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B-
X
#
0
S
F
d
e
h
c
t
a
L
5
t
i
B6
21
z
H
M
8
4
4
t
i
B5
21
z
H
M
4
2
3
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B
,
8
1
,
7
1
1
2
,
0
2
1)
9
:
2
1
(
M
A
R
D
S
1
t
i
B
,
9
2
,
8
2
2
3
,
1
3
1)
5
:
8
(
M
A
R
D
S
0
t
i
B
,
5
3
,
4
3
8
3
,
7
3
1)
1
:
4
(
M
A
R
D
S



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