AP32113 datasheet(13/38 Pages) INFINEON

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AP32113

Connecting Memory to the TC1130 External Bus Unit

(EBU)

Application Note

V1.0, 2006-02

2.4.2.4

Clock Feedback Enable

The sampling stages for flash read data (and WAIT) can be set to use a clock fed back

from the flash clock pin. This intended to increase operating speed by allowing a full

period of BFCLK for data to propagate from the flash to the data inputs of the first

sampling flip-flops. This does not allow use of an externally generated clock with burst

flash devices. This additional operating margin comes at the expense of increased

latency as the extra stages needed add two BFCLK cycles to the time required to access

data.

Clock feedback is enabled by setting BFCON.FDBKEN and the necessary latency is

programmed into the BFCON.DTALTNCY field. This must be 2*(n+1), where n is the

value in BFCON.EXTCLOCK.

2.4.2.5

Device Type Selection

BUSCON.CTYPE can be used to support different ways of connecting address

information to the burst flash. BUSCON.CTYPE=00B is for standard device

configurations with a separate address bus. When set to 01B, the address is driven onto

the data bus during the address and address hold phases of the access for those

devices with a multiplexed address and data bus. If BUSCON.PORTW=10B and

BUSCON.CTYPE=10B, the same 16 bit address is driven onto the upper and lower

halves of the data bus during the address and address hold phases. This is to enable the

use of 2, 16 bit wide, multiplexed devices to make a 32 bit wide memory region. If

BUSCON.PORTW=01B and BUSCON.CTYPE=11B, then the 16 LSBs of the address

are driven onto the upper 16 bits of the data bus for all phases of the access. This is a

pin saving mode intended to allow the use of a 16 bit standard burst flash with 32 bit

multiplexed devices without having to provide all the bits of a separate address bus. Note

that in all the multiplexed addressing modes, the address is still driven onto the address

bus pins for all phases of the access.

2.4.2.6

WAIT Signal Control

Without Wait

Operation

without

wait

configured

setting

BUSCON.WAIT=00B or

BFCON.WAITFUNC set to “terminate burst” (1) and BUSCON.WAIT to 01B or 10B. Note

that no devices have been found that operate successfully in “terminate burst” mode

unless BUSCON.WAIT is set to 10B. Also “terminate burst” is incompatible with clock

feedback.

In this mode, the burst flash controller will generate the exact number of burst phases

necessary to complete the requested access. To do this, it uses the opcode of the

transaction and the port width of the memory region being accesses (defined by

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