Data Sheet

ADRF5141

APPLICATIONS INFORMATION

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Rev. 0 | 11 of 13

The ADRF5141 has two power-supply pins (VDD and VSS) and

one control pin (CTRL). Figure 21 shows the external components

and connections for the supply and control pins. The VDD pin is

decoupled with 100 pF and 1000 pF multilayer ceramic capacitor,

while the VSS pin and the control pin are decoupled with 100

pF multilayer ceramic capacitor. The device pinout allows the place-

ment of the decoupling capacitors close to the device. No other

external components are needed for bias and operation, except

DC-blocking capacitors on the ANT, TX, and RX pins when the RF

lines are biased at a voltage different than 0 V. Refer to the Pin

Configuration and Function Descriptions section for details.

Figure 21. Recommended Schematic

The power limiter at the RX arm engages and limits the input

power from the ANT power. See the Table 1 section for the RX

flat Leakage power level. A typical application of the ADRF5141

is to connect an antenna at the ANT pin, a power amplifier (PA)

at the TX pin, and a low-noise amplifier (LNA) at the RX pin. The

integrated power limiter at the RX arm provides protection to the

LNA input connected to the RX pin (see Figure 22).

Figure 22. Typical Application Diagram

RECOMMENDATIONS FOR PCB DESIGN

The RF ports are matched to 50 Ω internally and the pinout is

designed to mate a coplanar waveguide (CPWG) with 50 Ω charac-

teristic impedance on the PCB. Figure 23 shows the referenced

CPWG RF trace design for an RF substrate with 8 mil thick Rogers

RO4003 dielectric material. RF trace with 14 mil width and 7 mil

clearance is recommended for 1.5 mil finished copper thickness.

Figure 23. Example PCB Stack-Up

Figure 24 shows the routing of the RF traces, supply, and control

signals from the device. The ground planes are connected with as

many filled, through vias as allowed for optimal RF and thermal

performance. The primary thermal path for the device is the bottom

side; therefore, a heatsink is required underneath the PCB to

ensure maximum heat dissipation and to reduce thermal rise on the

PCB during high-power applications.

Figure 24. PCB Routings

Figure 25 shows the recommended layout from the device RF pins

to the 50 Ω CPWG on the referenced stack-up. PCB pads are

drawn 1:1 to device pads. The ground pads are drawn soldermask

defined, and the signal pads are drawn as pad defined. The RF

trace from the PCB pad is extended with the same width till the

package edge and tapered to the RF trace with a 45° angle.

The paste mask is also designed to match the pad without any

aperture reduction. The paste is divided into multiple openings for

the paddle.