DPS1035

Document number: DS38925 Rev. 7 - 2

2 of 11

www.diodes.com

November 2019

© Diodes Incorporated

DPS1035

Typical Application Circuit

DPS1035

1

2

3

4

5

6

IN

IN

IN

EN

NC

GND

17

16

15

14

13

12

OUT

OUT

OUT

VLIM

NC

DV/DT

RVLIM

240k

Ω

CDV/DT

6.8nF

COUT

10

μF

CIN

10

μF

R3

10k

Ω

3.3V

OFF

ON

VEN

CVREG

0.1

μF

VIN

VOUT

SRC

CFLT

0.1

μF

Pin Descriptions

Pin Number

Pin Name

Type

Function

1, 2, 3

IN

P

Power Supply and Input Port.

4

EN

I

Enable. ‘0’ = device OFF; ‘1’ = device ON. This pin must not be left floating.

5, 11, 13

NC

—

No Connection. All NC pins must be left floating.

6

GND

GND

Device Ground

7

VREG

I/O

Voltage Regulator. A 0.1

μF capacitor is recommended between this pin and ground.

8

DISC1

I

IN Port Discharge Control.

’1’ = port voltage to be discharged; ‘0’ = disabled.

9

DISC2

I

OUT Port Discharge Control.

’1’ = port voltage to be discharged; ‘0’ = disabled.

10

FAULTB

O

Fault Status Indicator. An external pull-up resistor is required. This active-low pin shall be tied to

GND when not used.

12

DV/DT

I/O

Ramp-up Control. A capacitor between this pin and GND sets the ramp-up rate.

14

VLIM

I/O

Voltage Limit Setting. A resistor between this pin and GND sets the over-voltage limit of the IN port.

15, 16, 17

OUT

O

Output Port.

18

(Exposed Pad)

SRC

I/O

Common Source. The exposed pad of the V-QFN4040-17 package must not be connected to any

signal.