GD25Q41ASIGT datasheet(21/51 Pages) GIGADEVICE

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Uniform Sector

Dual and Quad Serial Flash

GD25Q21B

address is automatically incremented to the next higher address after each byte of data is shifted out.

Figure 11. Quad Output Fast Read Sequence Diagram

7.11.

Dual I/O Fast Read (BBH)

The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input

the 3-byte address (A23-0) and a

“Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in

during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The

command sequence is shown in followed Figure12. The first byte addressed can be at any location. The address is

automatically incremented to the next higher address after each byte of data is shifted out. To ensure optimum

performance the High Performance Mode (HPM) command (A3H) must be executed once, prior to the Dual I/O Fast Read

command.

Dual I/O Fast Read with

“Continuous Read Mode”

The Dual I/O Fast Read command can further reduce command overhead through setting the

“Continuous Read

Mode

” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next

Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The

command sequence is shown in followed Figure13. If the

“Continuous Read Mode” bits (M7-0) are any value other than

AXH, the next command requires the first BBH command code, thus returning to normal operation. A

“Continuous Read

Mode

” Reset command can be used to reset (M7-0) before issuing normal command.

Command

6BH

CS#

SCLK

SI(IO0)

SO(IO1)

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

34 35 36 37

38 39

Byte1

42 43 44 45

46 47

Dummy Clocks

WP#(IO2)

High-Z

HOLD#(IO3)

High-Z

CS#

SCLK

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

Byte2 Byte3 Byte4

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