ES25P40 datasheet(13/35 Pages) EXCELSEMI

13 / 35 page

ES I

Rev. 0D May 11 , 2006

ES25P40

Excel Semiconductor inc.

ADVANCED INFORMATION

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction

allows new values to be written to the Status Regis-

ter. Before it can be accepted, a Write Enable

(WREN) instruction must previously have been

executed. After the Write Enable (WREN) instruc-

tion has been decoded and executed, the device

sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is

entered by driving Chip Select (CS#) Low, followed

by the instruction code and the data byte on Serial

Data Input (SI).

The instruction sequence is shown in Figure 8.

The Write Status Register (WRSR) instruction has

no effect on bits b6, b5, b1 and b0 of the Status

Chip Select (CS#) must be driven High after the

eighth bit of the data byte has been latched in. If

not, the Write Status Register (WRSR) instruction is

not executed.

As soon as Chip Select (CS#) is driven High, the

self-timed Write Status Register cycle (whose dura-

tion is tw ) is initiated. While the Write Status Regis-

ter cycle is in progress, the Status Register may still

be read to check the value of the Write In Progress

(WIP) bit. The Write In Progress (WIP) bit is 1 dur-

ing the self-timed Write Status Register cycle, and

is 0 when it is completed. At some unspecified time

before the cycle is completed, the Write Enable

Latch (WEL) is reset.

The Write Status Register (WRSR) instruction

allows the user to change the values of the Block

Protect (BP2, BP1, BP0) bits, to define the size of

the area that is to be treated as read-only, as

defined in Table 1. The Write Status Register

(WRSR) instruction also allows the user to set or

reset the Status Register Write Disable (SRWD) bit

in accordance with the Write Protect (W#) signal.

The Status Register Write Disable (SRWD) bit and

Write Protect (W#) signal allow the device to be put

in the Hardware Protected Mode (HPM). The Write

Status Register (WRSR) instruction cannot be exe-

cuted once the Hardware Protected Mode (HPM) is

entered.

Figure 7. Status Register Format

SRWD

BP2

BP1

BP0

WEL

WIP

Status Register Write Disable

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

Figure 8. Write Status Register (WRSR) Instruction Sequence

Status Register In

SCK

CS#

Instruction

High Impedance

MSB

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