CYWUSB6935
Document #: 38-16008 Rev. *C
Page 17 of 33
Addr: 0x1C
REG_WAKE_EN
Default: 0x00
76
543
210
Reserved
Wakeup Enable
Figure 7-19. Wake Enable
Bit Name
Description
7:1 Reserved
These bits are reserved and should be written with zeroes.
0
Wakeup Enable Wakeup interrupt enable.
0 = disabled
1 = enabled
A wakeup event is triggered when the PD pin is deasserted and once the IC is ready to receive SPI communications.
Addr: 0x1D
REG_WAKE_STAT
Default: 0x01
76
543
210
Reserved
Wakeup Status
Figure 7-20. Wake Status
Bit
Name
Description
7:1
Reserved
These bits are reserved. This register is read-only.
0
Wakeup Status
Wakeup status.
0 = Wake interrupt not pending
1 = Wake interrupt pending
This IRQ will assert when a wakeup condition occurs. This bit is cleared by reading the Wake Status register (Reg
0x1D). This register is read-only.
Addr: 0x20
REG_ANALOG_CTL
Default: 0x00
76
5432
10
Reserved
Reg Write
Control
MID Read
Enable
Reserved
Reserved
PA Output
Enable
PA Invert
Reset
Figure 7-21. Analog Control
Bit
Name
Description
7
Reserved
This bit is reserved and should be written with zero.
6
Reg Write Control Enables write access to Reg 0x2E and Reg 0x2F.
1 = Enables write access to Reg 0x2E and Reg 0x2F
0 = Reg 0x2E and Reg 0x2F are read-only
5
MID Read Enable The MID Read Enable bit must be set to read the contents of the Manufacturing ID register (Reg 0x3C-0x3F).
Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. This bit should only be set when
reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F).
1 = Enables read of MID registers
0 = Disables read of MID registers
4:3
Reserved
These bits are reserved and should be written with zeroes.
2
PA Output Enable The Power Amplifier Output Enable bit is used to enable the PACTL pin for control of an external power amplifier.
1 = PA Control Output Enabled on PACTL pin
0 = PA Control Output Disabled on PACTL pin
1
PA Invert
The Power Amplifier Invert bit is used to specify the polarity of the PACTL signal when the PaOe bit is set high.
PA Output Enable and PA Invert cannot be simultaneously changed.
1 = PACTL active low
0 = PACTL active high
0
Reset
The Reset bit is used to generate a self-clearing device reset.
1 = Device Reset. All registers are restored to their default values.
0 = No Device Reset.
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