FLEX6000 datasheet(39/52 Pages) ALTERA

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Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet

tOD1

Output buffer and pad delay, slow slew rate = off, VCCIO = VCCINT

C1 = 35 pF (2)

tOD2

Output buffer and pad delay, slow slew rate = off, VCCIO = low voltage

C1 = 35 pF (3)

tOD3

Output buffer and pad delay, slow slew rate = on

C1 = 35 pF (4)

tXZ

Output buffer disable delay

C1 = 5 pF

tZX1

Output buffer enable delay, slow slew rate = off, VCCIO = VCCINT

C1 = 35 pF (2)

tZX2

Output buffer enable delay, slow slew rate = off, VCCIO = low voltage

C1 = 35 pF (3)

tZX3

IOE output buffer enable delay, slow slew rate = on

C1= 35 pF (4)

tIOE

Output enable control delay

tIN

Input pad and buffer to FastTrack Interconnect delay

tIN_DELAY

Input pad and buffer to FastTrack Interconnect delay with additional delay

turned on

tLOCAL

LAB local interconnect delay

tROW

Row interconnect routing delay

(5)

tCOL

Column interconnect routing delay

(5)

tDIN_D

Dedicated input to LE data delay

(5)

tDIN_C

Dedicated input to LE control delay

tLEGLOBAL

LE output to LE control via internally-generated global signal delay

(5)

tLABCARRY

Routing delay for the carry-out of an LE driving the carry-in signal of a

different LE in a different LAB

tLABCASC

Routing delay for the cascade-out signal of an LE driving the cascade-in

signal of a different LE in a different LAB

(6)

tDRR

interconnects

(7)

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