XIO2000 datasheet(100/150 Pages) TI

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PCI Express Extended Configuration Space

November 2005

SCPS097B

Table 5−1. PCI Express Extended Configuration Register Map (Continued)

OFFSET

VC arbitration table (phase 31 − phase 24)

18Ch

Reserved

190h – 1BCh

Port arbitration table for VC1 (phase 7 – phase 0)

1C0h

Port arbitration table for VC1 (phase 15 – phase 8)

1C4h

Port arbitration table for VC1 (phase 23 – phase 16)

1C8h

Port arbitration table for VC1 (phase 31 – phase 24)

1CCh

Port arbitration table for VC1 (phase 39 – phase 32)

1D0h

Port arbitration table for VC1 (phase 47 – phase 40)

1D4h

Port arbitration table for VC1 (phase 55 – phase 48)

1D8h

Port arbitration table for VC1 (phase 63 – phase 56)

1DCh

Port arbitration table for VC1 (phase 71 – phase 64)

1E0h

Port arbitration table for VC1 (phase 79 – phase 72)

1E4h

Port arbitration table for VC1 (phase 87 – phase 80)

1E8h

Port arbitration table for VC1 (phase 95 – phase 88)

1ECh

Port arbitration table for VC1 (phase 103 – phase 96)

1F0h

Port arbitration table for VC1 (phase 111 – phase 104)

1F4h

Port arbitration table for VC1 (phase 119 – phase 112)

1F8h

Port arbitration table for VC1 (phase 127 – phase 120)

1FCh

Reserved

200h – FFCh

5.1

Advanced Error Reporting Capability ID Register

This read-only register identifies the linked list item as the register for PCI Express advanced error reporting

capabilities. The register returns 0001h when read.

PCI Express extended register offset:

100h

Read-only

Default value:

0001h

BIT NUMBER

RESET STATE

5.2

Next Capability Offset/Capability Version Register

This read-only register identifies the next location in the PCI Express extended capabilities link list. If bit 12

(VC_CAP_EN) in the general control register (offset D4h, see Section 4.65) is 0b, then the upper 12 bits in

this register are 000h, indicating the end of the linked list. If VC_CAP_EN is 1b, then the upper 12 bits in this

significant bits identify the revision of the current capability block as 1h.

PCI Express extended register offset:

102h

Read-only

Default value:

XX01h

BIT NUMBER

RESET STATE

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