CS5336 datasheet(8/34 Pages) CIRRUS

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low, ICLKD is divided by 2 to generate OCLKD.

The phase relationship between ICLKD and

OCLKD is always the same, and is shown in the

Switching Characteristics Timing Diagrams.

When CMODE is high, OCLKD is ICLKD di-

vided by 3. There are two possible phase

relationships between ICLKD and OCLKD,

which depend on the start-up timing between

DPD and L/R, shown in Figure 2.

Serial Data Interface

The serial data output interface has 3 possible

modes of operation: MASTER mode, SLAVE

mode with FSYNC high, and SLAVE mode with

FSYNC controlled. In MASTER mode, the A/D

converter is driven from a master clock (ICLKD)

and outputs all other clocks, derived from ICLKD

(see Figure 3). Notice the one SCLK cycle delay

between L/R edges and FSYNC rising edges.

FSYNC brackets the 16 data bits for each chan-

nel.

In SLAVE mode, L/R and SCLK are inputs. L/R

must be externally derived from ICLKD, and

should be equal to the Output Word Rate. SCLK

should be equal to the input sample rate, which is

equal to OCLKD/2. Other SCLK frequencies are

possible, but may degrade dynamic range because

of interference effects. Data bits are clocked out

via the SDATA pin using the SCLK and L/R in-

puts. The rising edge of SCLK causes the ADC to

Output

16 17 18 19 20 21

Output

Left Audio Data

Tag Bits

Left Data Tag

Right Audio Data

Tag Bits

Right Data Tag

* SCLK for CS5336/8.

SCLK inverted for

CS5339

FSYNC

Output

15 14

T2 T1 T0

15 14

T2 T1 T0

SDATA

Output

SCLK

L/ R

Figure 3. Data Output Timing - MASTER mode

Figure 4. Data Output Timing - SLAVE Mode, FSYNC high

Input

16 17 18 19 20

16 17 18 19 20 21

Input

FSYNC

Input (high)

SCLK

L/ R

Left Audio Data

Tag Bits

Left Data Tag

Right Audio Data

Tag Bits

Right Data Tag

15 14

T2 T1 T0

15 14

T2 T1 T0

SDATA

Output

* SCLK for CS5336/8.

SCLK inverted for

CS5339

CS5336, CS5338, CS5339

3-46

DS23F1

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