APR348

Document number: DS42016 Rev. 5 - 2

6 of 9

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March 2021

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APR348

Synchronous Rectification Principle Description (continued)

The Value and Meaning of Rx Resistance

After the secondary rectifier stops conduction with DCM operation, the primary MOSFET drain-to-source generates a ringing waveform, which results

from the resonant of primary inductance and equivalent switch-device output capacitance. This ringing waveform most likely leads to the synchronous

rectifier fault conduction. APR348 integrates an accurate turn-on voltage threshold and internal judge criteria to determine whether synchronous

rectification MOSFET can turn on or not. Rx is an external resistor, which multiplies with an internal current source to generate an accurate reference

for turn-on threshold judgment. Proposed to use 30k

Ω to 40kΩ resistance for Rx value.

Synchronous Rectification Forward Regulation and Turn-Off Stage

Once the synchronous rectification gate outputs high levels and the synchronous rectification MOSFET turns on, the secondary-side current goes

through synchronous rectification MOSFET. The voltage drop on synchronous rectification MOSFET is found by RDS(ON) × secondary-side current.

After minimum turn-on time tONMIN, the IC continuously monitors VDS by the VDET pin and generates a pull-down current from the MOSFET gate

until VDET > -45mV. The MOSFET drain-to-source voltage would remain at around -45mV with the secondary-side current decreasing. Real MOSFET

gate voltage depends on the MOSFET characteristics and drain current. When the primary MOSFET turns on, the secondary VDS would rise up.

Once VDET rises to trigger the turn-off threshold, the gate signal will be pulled down to GND. The synchronous rectification MOSFET gate voltage

drops quickly from a low voltage to zero after a very short turn-off delay.

Light Load Mode (LL Mode)

The APR348 provides light-load mode when the system goes into burst or no-load condition with interval-time pulses for low standby loss. The IC

internal has two timers, one is 640µs and the other is 2.5ms. When the interval time is between 640µs and 2.5ms, the gate drive outputs will skip

the first two cycles. When the interval time is over 2.5ms, gate drive outputs will skip the first eight cycles.

VDD Regulator and UVLO Protection

The VDD is an internal linear regulator output. When the synchronous rectification MOSFET and the IC are connected in low side, the VDD is supplied

by both VDET pin and VCC pin. When synchronous rectification MOSFET and IC are connected in high side, the VDD is supplied only via VDET. A

large capacitor (typical 4.7µF) at VDD pin is proposed for system design. The APR348 also has the UVLO protection. When VDD drops below

VDD_UVLO, the IC will stop working.