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STPW12 датащи(PDF) 15 Page - STMicroelectronics |
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STPW12 датащи(HTML) 15 Page - STMicroelectronics |
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15 / 23 page ![]() 8 Application guidelines 8.1 Power supply voltage The device is designed and optimized to work on 12 V power rails, even if the operating supply voltage can range from 10.5 V to 18 V. The maximum accuracy of the main operating features is reached for an input voltage of 12 V, therefore the operation at lower or higher voltages implies some small variations in the characteristic performance. 8.2 Input and output capacitors Input and output capacitors are mandatory to guarantee the device control loop stability and reduce the transient effects of stray inductances present in the input and output power paths. In fact when the STPW12 quickly interrupts the current flow due to power limit or thermal shutdown events, input inductance generates a positive voltage spike on the input pin and, at same way, the output inductance generates a negative voltage spike on the output. Such spikes might overcome the absolute maximum voltage ratings of the device and damage the device itself. To reduce the effects of such transients, CIN capacitor with a minimum value of 10 μF must be connected between the input pin and GND and placed as close as possible to the device. For the same reason, COUT capacitor has to be connected on the output port. The recommended value is 10 μF, if this is compatible with the required PWM operating frequency. When the device is supplied via a power line made of very long wires, where input inductance is higher than 3-4 μH, the input capacitance should be increased to 47 μF or more. See also next paragraph for additional information about protection. 8.3 Additional protections and layout guidelines Recommended additional protections and methods to address the input/output voltage spikes are the following: – Minimizing inductance of the input and output tracks, by making short and well dimensioned power traces. – Using TVS diodes on the input to absorb inductive spikes. – Schottky diode on the output to absorb negative spikes (for instance the STPS2L30). – Using a ground plane to connect the GND terminal of the IC (exposed pad) to the system GND. The CS capacitor, used for the selection of the auto-retry delay time, is charged by a low 160 nA (typ.) current. To minimize the effect of noisy signals present on this PCB on the Cset pin, resulting in incorrect delay time, the capacitor should be placed as close as possible to the IC pin and GND. STPW12 Application guidelines DS12478 - Rev 1 page 15/23 |
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