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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS47L63 датащи(PDF) 23 Page - Cirrus Logic |
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CS47L63 датащи(HTML) 23 Page - Cirrus Logic |
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23 / 300 page  23 DS1085F3 CS47L35 3 Characteristics and Specifications Table 3-21. SLIMbus Interface Timing The following timing information is valid across the full range of recommended operating conditions. Parameter 1 1.SLIMbus interface timing. Symbol Minimum Typ Maximum Units SLIMCLK input SLIMCLK cycle time SLIMCLK pulse width high SLIMCLK pulse width low — TCLKH TCLKL 35 12 12 — — — — — — ns ns ns SLIMCLK output SLIMCLK cycle time SLIMCLK pulse width high SLIMCLK pulse width low — TCLKH TCLKL 40 12 12 — — — — — — ns ns ns SLIMCLK slew rate (20%–80%) CLOAD = 15 pF, SLIMCLK_DRV_STR = 0 CLOAD = 70 pF, SLIMCLK_DRV_STR = 0 CLOAD = 70 pF, SLIMCLK_DRV_STR = 1 SRCLK SRCLK SRCLK 0.09 x VDBVDD1 0.02 x VDBVDD1 0.04 x VDBVDD1 — — — 0.22 x VDBVDD1 0.05 x VDBVDD1 0.11 x VDBVDD1 V/ns V/ns V/ns SLIMDAT input SLIMDAT setup time to SLIMCLK falling edge TSETUP 3.5 — — ns SLIMDAT hold time from SLIMCLK falling edge TH 2— — ns SLIMDAT output SLIMDAT time for data output valid (relative to SLIMCLK rising edge) SLIMDAT_DRV_STR = 0, DBVDD1 = 1.71 V CLOAD = 15 pF, SLIMDAT_DRV_STR = 1, DBVDD1 = 1.71 V CLOAD = 30 pF, SLIMDAT_DRV_STR = 0, DBVDD1 = 1.71 V CLOAD = 30 pF, SLIMDAT_DRV_STR = 1, DBVDD1 = 1.71 V CLOAD = 50 pF, SLIMDAT_DRV_STR = 0, DBVDD1 = 1.71 V CLOAD = 50 pF, SLIMDAT_DRV_STR = 1, DBVDD1 = 1.71 V CLOAD = 70 pF, SLIMDAT_DRV_STR = 0, DBVDD1 = 1.71 V CLOAD = 70 pF, SLIMDAT_DRV_STR = 1, DBVDD1 = 1.71 V TDV TDV TDV TDV TDV TDV TDV TDV — — — — — — — — 4.7 4.3 6.8 5.8 9.6 7.9 12.4 10.0 8.1 7.3 11.8 10.0 16.6 13.7 21.5 17.4 ns ns ns ns ns ns ns ns SLIMDAT slew rate (20%–80%) CLOAD = 15 pF, SLIMDAT_DRV_STR = 0 CLOAD = 30 pF, SLIMDAT_DRV_STR = 0 CLOAD = 30pF, SLIMDAT_DRV_STR = 1 CLOAD = 70pF, SLIMDAT_DRV_STR = 0 CLOAD = 70pF, SLIMCLK_DRV_STR = 1 SRDATA SRDATA SRDATA SRDATA SRDATA — — — — — — — — — — 0.64 x VDBVDD1 0.35 x VDBVDD1 0.46 x VDBVDD1 0.16 x VDBVDD1 0.21 x VDBVDD1 V/ns V/ns V/ns V/ns V/ns Other parameters Driver disable time TDD —— 6 ns Bus holder output impedance 0.1 x VDBVDD1 <V< 0.9 x VDBVDD1 RDATAS 18 — 50 kΩ Notes: • The signal timing information describes the timing requirements of the SLIMbus interface as a whole, not just the CS47L35 device. • TDV is the propagation delay from the rising SLIMCLK edge (at CS47L35 input) to the SLIMDAT output being achieved at the input to all devices across the bus. • TSETUP is the set-up time for SLIMDAT input (at CS47L35), relative to the falling SLIMCLK edge (at CS47L35). • TH is the hold time for SLIMDAT input (at CS47L35) relative to the falling SLIMCLK edge (at CS47L35). • For more details of the interface timing, refer to the MIPI Alliance Specification for Serial Low-power Inter-Chip Media Bus (SLIMbus) SLIMDAT TDV TCLKL TCLKH VIH VIL TSETUP TH VIH, VOH VIL, VOL SLIMCLK VIL, VIH are the 35%/65% levels of the respective inputs. VOL, VOH are the 20%/80% levels of the respective outputs. The SLIMDAT output delay (TDV) is with respect to the input pads of all receiving devices. |
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