3.15

Direct Memory Access (DMA)

The DMAC is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral.

The DMAC is an AMBA AHB module, and connects to the Advanced High-performance Bus (AHB).

Module key features:

•

Eight DMA channels. Each channel can support an unidirectional transfer.

•

The DMAC provides 32 peripheral DMA request lines.

•

Single DMA and burst DMA request signals.

•

Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers.

•

Scatter or gather DMA support through the use of linked lists.

•

Hardware DMA channel priority. DMA channel 0 has the highest priority and channel 31 has the lowest

priority.

•

If requests from two channels become active at the same time, the channel with the highest priority is

serviced first.

•

AHB slave DMA programming interface to the DMA control registers.

•

Two AHB bus masters for transferring data.

•

Programmable DMA burst size.

•

Working on AHB clock.

3.16

Antenna sensing

The following figures show how the antenna sensing circuit works. SENSE1 and SENSE2 input voltage range

must be between VRF_IN and GND.

Figure 3. Antenna sensing configuration when antenna is supplied with 3.3 V

Antenna

matching network

LNA_IN

SENSE2

SENSE1 3V3

V_ant = 3.3V

choke

R

SENSE<1>

SENSE<0>

Antenna sensing detection in STA8135GA uses two comparators with hysteresis. If the antenna is supplied with a

voltage of 3.3 V the antenna sensing can be connected as showed in the picture.

In the following tables are showed thresholds when current is rising and when is falling with R = 1.4 Ω and

V_ant = 3.3 V.

Table 10. Antenna sensing current - power rising

Current from antenna (when current is rising)

SENSE <1>

SENSE <0>

I < 24 mA

0

0

24 ≤ I ≤ 62 mA

0

1

I > 62 mA

1

1

STA8135GA

Direct Memory Access (DMA)

DB4575 - Rev 1

page 17/29