SPSB0813 datasheet(118/135 Pages) STMICROELECTRONICS

118 / 135 page

Bit

Name

Description

•

access to undefined address

•

Write operation to status register

•

DI stuck at '0' or '1'

•

CSN timeout

•

Parity failure

•

invalid or undefined setting

The SPI frame is ignored

Bit is latched until a “Read and clear” command

SPI SCK CNT

SPI clock counter

‘1’ indicates that an SPI frame with the wrong number of CLK cycles was detected

Bit is latched until a valid SPI frame

V1_OV

V1 overvoltage

‘1’ indicates the voltage at V1 has reached the overvoltage threshold

Bit is latched until a “Read and clear” command

Thermal warning

‘1’ indicates that the temperature has reached the thermal warning threshold

Bit is latched until a “Read and clear” command

V2SC

V2 short circuit detection

‘1’ indicates that a short circuit to GND condition of V2 at turn-on of the regulator

(V2 < V2_fail for t > tv2_short)

Bit is latched until a “Read and clear” command

V2FAIL

V2 failure detection

‘1’ indicates that a V2 fail event occurred since last readout

(V2 < V2_fail for t > tv2_fail)

Bit is latched until a “Read and clear” command

V1FAIL

V1 failure detection

‘1’ indicates that a V1 fail event occurred since last readout

(V1 < V1_fail for t > tv1_fail)

Bit is latched until a “Read and clear” command

RES

Reserved

VSREG_OV

VSREG overvoltage

‘1’ indicates that the voltage at VSREG has reached the overvoltage threshold

Bit is latched until a “Read and clear” command

VSREG_UV

VSREG undervoltage

‘1’ indicates that the voltage at VSREG has reached the undervoltage threshold

Bit is latched until a “Read and clear” command

VS_OV

Vs overvoltage

‘1’ indicates that the voltage at Vs has reached the overvoltage threshold

Bit is latched until a “Read and clear” command

VS_UV

Vs undervoltage

‘1’ indicates that the voltage at Vs has reached the undervoltage threshold

Bit is latched until a “Read and clear” command

SPSB081

Status registers

DS14048 - Rev 1

page 118/135

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