SPSB0813 datasheet(117/135 Pages) STMICROELECTRONICS

117 / 135 page

Table 115. Status register SR2 (0x32)

Bit

name

Access

R&C

Table 116. SR2 description

Bit

Name

Description

LIN_PERM_DOM

LIN bus signal is dominant for t > Tdom(bus)

Bit is latched until a “Read and clear” command

LIN_TXD_DOM

TxD_L pin is dominant for t > tdom(TXDL)

The LIN transmitter is disabled until the bit is cleared

Bit is latched until a “Read and clear” command

LIN_PERM_REC

LIN bus signal does not follow TxD_L within tLIN

The LIN transmitter is disabled until the bit is cleared

Bit is latched until a “Read and clear” command

CAN_RXD_REC

RxD_C has not followed TxD_C for 4 times

The CAN transmitter is disabled until the bit is cleared

Bit is latched until a “Read and clear” command

CAN_PERM_REC

CAN bus signal did not follow TxD_C for 4 times

The CAN transmitter is disabled until the bit is cleared

Bit is latched until a “Read and clear” command

CAN_PERM_DOM

CAN bus signal is dominant for t > tCAN

Bit is latched until a “Read and clear” command

CAN_TXD_ DOM

TxD_C pin is dominant for t > tdom(TXDC)

The CAN transmitter is disabled until the bit is cleared

Bit is latched until a “Read and clear” command

CANTO

CAN communication timeout

Bit is set if there is no communication on the bus for t > tSilence

CANTO indicates that there was a transition from BIASON to BIASOFF

Bit is latched until a read and clear access

FORCED_SLEEP_V1

Device entered forced sleep mode due to an overvoltage occurrence on V1

Bit is latched until a “Read and clear” command

RES

Reserved

RES

Reserved

RES

Reserved

SPI INV CMD

Invalid SPI command

‘1’ indicates one of the following conditions was detected:

SPSB081

Status registers

DS14048 - Rev 1

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