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SPSB081 датащи(PDF) 48 Page - STMicroelectronics |
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SPSB081 датащи(HTML) 48 Page - STMicroelectronics |
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48 / 135 page ![]() ROM address Description Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 12H <WD type 2> R → 91H 11H <WD type 1> R → 3CH 10H <SPI mode> R → B0H … → 0AH <silicon Ver.> R → major revision minor revision … → 05H <device No.4> R → 50H 04H <device No.3> R → 37H 03H <device No.2> R → 52H 02H <device No.1> R → 55H 01H <device family> R → 01H 00H <company code> R → 00H 4.3.1.1 Device identification registers These registers represent a unique signature to identify the device and silicon version. <Company Code>: 00H (STMicroelectronics) <Device Family>: 01H (BCD power management) <Device No. 1>: 55H (ASCII code for U) <Device No. 2>: 52H (ASCII code for R) <Device No. 3>: 37H (ASCII code for 7) <Device No. 4>: 50H (ASCII code for P) 4.3.1.2 SPI modes By reading out the <SPI mode> register general information of SPI usage of the device application registers can be read. Table 20. SPI mode register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BR DL2 DL1 DL0 0 0 S1 S0 1 0 1 1 0 0 0 0 <SPI mode>: B0H (burst mode read available, 32 bit, no data consistency check). 4.3.1.3 SPI burst read Table 21. Burst read bit Bit 7 Description 0 BR not available 1 BR available The SPI burst read bit indicates if a burst read operation is implemented. The intention of a burst read is, for example, used to perform a device internal memory dump to the SPI master. The start of the burst read is like a normal read operation. The difference is, that after the SPI data length the CSN is not pulled high and the SCK is continuously clocked. When the normal SCK max count is reached (SPI data length), the consecutive addressed data is latched into the shift register. This procedure is performed every time when the SCK payload length is reached. SPSB081 Address definition DS14048 - Rev 1 page 48/135 |
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